Jitter Tolerance Acceleration Using the Golden Section Optimization Technique

Post-silicon validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of computer platforms under the current time-to-market (TTM) commitments. The goal of post-silicon validation for HSIO links is to confirm design robustness of both receiver (Rx) and transmitter (Tx) circuitry in a real application environment. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) through the link under worst stressing conditions. However, JTOL testing is very time-consuming when executing at specification BER, and the testing time is extremely increased when considering manufacturing process, voltage, and temperature (PVT) test coverage for a qualification decision. In order to speed up this process, we propose a new approach for JTOL testing based on the golden section algorithm. The proposed method takes advantage of the fast execution of the golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are seen. Our proposed methodology is validated by implementing it in a server HSIO link

Fast jitter tolerance testing for high-speed serial links in post-silicon validation

Post-silicon electrical validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of high-performance computer platforms under current aggressive time-to-market (TTM) commitments. Improvements in signaling methods, circuits, and process technologies have allowed HSIO data rates to scale well beyond 10 Gb/s. Noise and EM effects can create multiple signal integrity problems, which are aggravated by continuously faster bus technologies. The goal of post-silicon validation for HSIO links is to ensure design robustness of both receiver (Rx) and transmitter (Tx) circuitry in real system environments. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) of the link under worst stressing conditions. However, JTOL testing is extremely time-consuming when executed at specification BER considering manufacturing process, voltage, and temperature (PVT) test coverage. In order to significantly accelerate this process, we propose a novel approach for JTOL testing based on an efficient direct search optimization methodology. Our approach exploits the fast execution of a modified golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are found. Our proposed methodology is validated in a realistic industrial server post-silicon validation platform for three different computer HSIO links: SATA, USB3, and PCIe3.ITESO, A.C