Multi-Softcore Architecture on FPGA

To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs) are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication)

Autonomna navigacija za invalidska kolica s detekcijom prepreka u stvarnom vremenu korištenjem 3D senzora

Autonomous wheelchairs operating in dynamic environments need to sense its surrounding environment and adapt the control signal, in real-time, to avoid collisions and protect the user. In this paper we propose a robust, simple and real-time autonomous navigation module that drives a wheelchair toward a desired target, along with its capability to avoid obstacles in a 3D dynamic environment. To command the mobile robot to the target, we use a Fuzzy Logic Controller (FLC). For obstacle avoidance, we use the Kinect Xbox 360 to provide an actual map of the environment. The generated map is fed to the reactive obstacle avoidance control Deformable Virtual Zone (DVZ). Simulations and real world experiments results are reported to show the feasibility and the performance of the proposed control system.Autonomna invalidska kolica koja se kreću u dinamičkim okruženjima moraju biti sposobna detektirati prepreke u svojoj okolini, te prilagoditi upravljački signal u stvarnom vremenu kako bi se izbjegli sudari i zaštitio korisnik. U ovom radu predlaže se jednostavan, robustan modul za autonomnu navigaciju u stvarnom vremenu koji vodi invalidska kolica prema željenom odredištu, te omogućuje izbjegavanje prepreka u 3D okruženju. Za upravljanje koristi se regulator baziran na neizravnoj logici (FLC). Za izbjegavanje prepreka koristi se Kinect Xbox 360 senzor koji gradi kartu okoline. Generirana karta se predaje reaktivnoj kontroli za izbjegavanje prepreka Deformiranoj Virutalnoj Zoni (DVZ). Prikazani su rezultati simulacija i eksperimenata u stvarnom svijetu kako bi se pokazala izvedivost i kvaliteta izvođenja predloženog sustava upravljanja

Mppsocgen: A framework for automatic generation of mppsoc architecture

Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures.Comment: 16 pages; International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 201

DESAGREGATION DES ACCRUALS DISCRETIONNAIRES ET PERTINENCE DU BENEFICE COMPTABLE

De nombreux travaux récents ont mis en évidence le rôle informationnel des accruals en général et ceux des accruals discrétionnaires en particulier. Certains ont testé cette relation d'une manière directe en étudiant l'effet des accruals sur la pertinence des bénéfices. D'autres l'ont fait d'une manière indirecte en étudiant leur effet sur les cash flows futurs ou sur la valeur de l'entreprise. Toutefois, aucune recherche ne s'est posée la question de voir si la désagrégation des accruals discrétionnaires augmenterait le pouvoir explicatif et prédictif du bénéfice. Les résultats de notre étude ont montré que les accruals discrétionnaires sont valorisés par les investisseurs français et que la désagrégation de ce type d'accruals améliore la pertinence du bénéfice comptable.accruals discrétionnaires; désagrégation; pertinence du bénéfice comptable

Broadcast with mask on a Massively Parallel Processing on a Chip

workshop drnoc2012The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), where the processing stage and that of setting up the communication mechanism need several clock periods. Subnetting is the strategy used to partition a single physical network into more than one smaller logical sub-networks (subnets). This technique better controls the broadcast instructions domain and the data traffic between network nodes. Furthermore, it allows to separate synchronous communications from asynchronous processing which maintains reliable communications and rapid processing through parallel processors. This paper describes the design of a communication model called broadcast with mask. This model is dedicated to mppSoC architecture with a huge number of processor elements because it maintains performances even when the number of processors increases. Simulation results and an FPGA implementation validate our approach

Conception des chaînes logistiques multicritères avec prise en compte des incertitudes

Les modèles de conception des chaînes logistiques sont devenus de plus en plus complexes, à cause de l'environnement économique incertain et l'introduction de nouveaux critères de décision tels que : l'aspect environnemental, l'aspect social, l'aspect législatif, l'aspect économique, la satisfaction du client et la prise en compte des risques. Répondre aux changements qui touchent les chaînes logistiques exige de composer avec des incertitudes et des informations incomplètes. Configurer des chaînes logistiques multicritères avec prise en compte des incertitudes peut garantir la continuité des activités de l'entreprise.L'objectif principal de cette thèse est la conception de chaînes logistiques multicritères qui résistent aux changements et l'instabilité des marchés. Le manuscrit de cette thèse s'articule autour de sept principaux chapitres:1 - introduction.2 - Etat de l'art sur la conception des chaînes logistiques.3 -Conception des chaînes logistiques multicritères en mesure de répondre aux nouveauxcritères économiques, sociaux, environnementaux et législatifs.4 - Conception des chaînes logistiques multi-objectifs.5 - Développement d'une heuristique de résolution des problèmes de conception deschaînes logistiques de taille réelle.6 - Conception des chaînes logistiques avec prise en compte des incertitudes.7 - Conclusions et perspectives.This thesis contributes to the debate on how uncertainty and concepts of sustainable development can be put into modern supply chain network and focuses on issues associated with the design of multi-criteria supply chain network under uncertainty. First, we study the literature review , which is a review of the current state of the art of Supply Chain Network Design approaches and resolution methods. Second, we propose a new methodology for multi-criteria Supply Chain Network Design (SCND) as well as its application to real Supply Chain Network (SCN), in order to satisfy the customers demand and respect the environmental, social, legislative, and economical requirements. The methodology consists of two different steps. In the first step, we use Geographic Information System (GIS) and Analytic Hierarchy Process (AHP) to buildthe model. Then, in the second step, we establish the optimal supply chain network using Mixed Integer Linear Programming model (MILP). Third, we extend the MILP to a multi-objective optimization model that captures a compromisebetween the total cost and the environment influence. We use Goal Programming approach seeking to reach the goals placed by Decision Maker. After that, we develop a novel heuristic solution method based on decomposition technique, to solve large scale supply chain network design problems that we failed to solve using exact methods. The heuristic method is tested on real case instances and numerical comparisons show that our heuristic yield high quality solutions in very limited CPU time. Finally, again, we extend the MILP model presented before where we assume that the costumer demands are uncertain. We use two-stage stochastic programming approach to model the supply chain network under demand uncertainty. Then, we address uncertainty in all SC parameters: opening costs, production costs, storage costs and customers demands. We use possibilistic linear programming approach to model the problem and we validate both approaches in a large application case.ARRAS-Bib.electronique (620419901) / SudocSudocFranceF

Defensive Approximation: Securing CNNs using Approximate Computing

In the past few years, an increasing number of machine-learning and deep learning structures, such as Convolutional Neural Networks (CNNs), have been applied to solving a wide range of real-life problems. However, these architectures are vulnerable to adversarial attacks. In this paper, we propose for the first time to use hardware-supported approximate computing to improve the robustness of machine learning classifiers. We show that our approximate computing implementation achieves robustness across a wide range of attack scenarios. Specifically, for black-box and grey-box attack scenarios, we show that successful adversarial attacks against the exact classifier have poor transferability to the approximate implementation. Surprisingly, the robustness advantages also apply to white-box attacks where the attacker has access to the internal implementation of the approximate classifier. We explain some of the possible reasons for this robustness through analysis of the internal operation of the approximate implementation. Furthermore, our approximate computing model maintains the same level in terms of classification accuracy, does not require retraining, and reduces resource utilization and energy consumption of the CNN. We conducted extensive experiments on a set of strong adversarial attacks; We empirically show that the proposed implementation increases the robustness of a LeNet-5 and an Alexnet CNNs by up to 99% and 87%, respectively for strong grey-box adversarial attacks along with up to 67% saving in energy consumption due to the simpler nature of the approximate logic. We also show that a white-box attack requires a remarkably higher noise budget to fool the approximate classifier, causing an average of 4db degradation of the PSNR of the input image relative to the images that succeed in fooling the exact classifierComment: ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2021

IP based configurable SIMD massively parallel SoC

International audienceSignificant advances in the field of configurable computing have enabled parallel processing within a single Field- Programmable Gate Array (FPGA) chip. This paper presents the implementation of a flexible and programmable Single Instruc- tion Multiple Data (SIMD) processing system on FPGA that can be adapted to the application. Its implementation is based on an IP (Intellectual Property) assembling approach making its design fast and easy. A generation tool is also developed to generate the SIMD configuration depending on the application requirements. The proposed parallel processing system on chip is portable, scalable and flexible since it can be customized to match the needs of a data parallel application. Based on FPGA, different SIMD configurations have been evaluated in terms of performance and area trade-offs. The proposed parametric system shows good results executing some signal processing applications such as parallel matrices multiplication, FIR filter and RGB to YIQ image color conversion