Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs

In this paper, we systematically evaluate dc/ac performances of sub-7-nm node fin field-effect transistors (FinFETs) and nanosheet FETs (NSEETs) using fully calibrated 3-D TCAD. The stress effects of all the devices were carefully considered in terms of carrier mobility and velocity averaged within the active regions. For detailed AC analysis, the parasitic capacitances were extracted and decomposed into several components using TCAD RF simulation platform. FinFETs improved the gate electrostatics by decreasing fin widths to 5 nm, but the fin heights were unable to improve RC delay due to the trade-off between on-state currents and gate capacitances. The NSEETs have better on-state currents than do the FinFETs because of larger effective widths (W-eff) under the same device area. Particularly p-type NSEETs have larger compressive stress within the active regions affected by metal gate encircling all around the channels, thus improving carrier mobility and velocity much. On the other hand, the NSEETs have larger gate capacitances because larger W-eff increase the gate-to-source/drain overlap and outer-fringing capacitances. In spite of that, sub-7-nm node NSEETs attain better RC delay than sub-7-nm node as well as 10-nm node FinFETs for standard and high performance applications, showing better chance for scaling down to sub-7-nm node and beyond.11Ysciescopu

Bottom oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node

Structural advancements of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) without punch-through-stopper (PTS) were introduced using fully calibrated TCAD for the first time. It is challenging to scale down conventional bulk FinFETs into 5-nm technology node due to the sub-fin leakage increase. Meanwhile, bottom oxide deposition after anisotropic etching for source/drain (S/D) epi formation prevents the sub-fin leakage effectively even without the PTS doping, thus achieving better gate-to-channel controllability. Bottom oxide FinFETs also have smaller gate capacitances than do conventional FinFETs because the parasitic capacitances decrease by smaller S/D epi separated from the bottom Si layer, which reduces junction and outer-fringing capacitances. But smaller S/D epi decreases the stresses along the channel direction, and the effective widths decrease by the bottom oxide layer blocking the current paths at the bottom side of fin channels. Furthermore, increase of the interconnect resistance and capacitance parasitics down to 5-nm node diminishes the improvements of total delays as the interconnect wire length increases greatly. In spite of these drawbacks, 5-nm node bottom oxide FinFETs achieve smaller total delays than do the 7-nm node conventional FinFETs, especially for low-power applications, thus promising for the scalability of bulk FinFETs along with simple and reliable process by avoiding PTS step.11Ysciescopu

Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

A novel and feasible process scheme to downsize the source/drain (S/D) epitaxy of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) were introduced by using fully-calibrated TCAD for the first time. The S/D epitaxy formed by selective epitaxial growth was diamond-shaped and occupied a large proportion of the device size irrespective of the active channel area. However, this problem was solved by patterning the low-k regions prior to S/D formation by preventing the lateral overgrowth of S/D epitaxy; the so-called S/D patterning (SDP). Its smaller S/D epitaxy decreased the average longitudinal channel stresses and drive currents for NFETs. However, the small diffusions of the boron dopants into the channel regions improved the short-channel effects and alleviated the drive current reduction for PFETs. Gate capacitances decreased greatly by reducing outer-fringing capacitances between the metal-gate stack and S/D regions. Through SPICE simulation based on the virtual source model, operation frequencies and dynamic powers of 15-stage ring oscillators were studied. SDP FinFETs have better circuit performances than the conventional and bottom oxide bulk FinFETs along with smaller active areas, promising for further area scaling through simple and reliable S/D process.11Ysciescopu

Gate-All-Around FETs: Nanowire and Nanosheet Structure

DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications

Si Gate-All-Around Nanosheet FET: the Key Enabler of 3nm Technology Node

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Learning-Based Ordering Characters on Ancient Document

Digitalizing and translating a scanned document image entails detecting the characters using a detector and translating the characters in the order they were detected with a translator. However, it is impossible to translate these characters correctly because the detector often detects them in any order. As a result, since it is critical to organize the recognized characters for proper translation, we propose ordering characters from documents with multiple variations using the strength of the learning-based model that learns the necessary operations from the data. In this task, it is difficult to order the characters written on antique handwritten documents that have deviations such as a bent or split line, as opposed to official records that have lines placed uprightly one by one. Because dealing with these many variants using a human-designed algorithm is problematic, we arrange characters printed on papers with diverse variations by taking advantage of a training model that can learn the appropriate function from data. Our method outputs both line id and y-axis and combines them to assign the sequential index. It is difficult to train using simply local regions because sequential character indexes in a large range include long-range dependencies. To solve this problem, we use network architecture to expand the receptive field as wide as possible. The network must learn to give various indexes to characters in similar places for each document because the number and area of characters vary for each document. We offer the ground truth assign method based on the absolute position to assign similar indexes to characters in similar places. Furthermore, even if the network uses absolute ground truth, the network may assign the incorrect line if the center coordinates of characters are biased in one direction. As a result, we employed the Region of Interest (ROI) from the pretrained coordinate layer, which contains position and trend information. We used the modified edit distance to compare the similarity of character indexes from the ground truth and our technique. In addition, we computed the modified fisher criterion to assess the degree of the clustering line. Consequently, our edit distance is just 0.43 times that of the human-designed algorithm, and our fisher criterion is 1.46 times that of the human-designed algorithm, improving the performance of human-designed algorithm.11Nsciescopu

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (G(m)) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (Ro) by dual-WF scheme and thus achieve larger intrinsic gain (A(V) = G(m)R(o)). Smaller G(m) and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large R-o increases the maximum frequency (F-max). Especially, 2-CAS has larger A(V) and F-max than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.11Ysciescopu

Arbitrary Font Generation by Encoder Learning of Disentangled Features

Making a new font requires graphical designs for all base characters, and this designing process consumes lots of time and human resources. Especially for languages including a large number of combinations of consonants and vowels, it is a heavy burden to design all such combinations independently. Automatic font generation methods have been proposed to reduce this labor-intensive design problem. Most of the methods are GAN-based approaches, and they are limited to generate the trained fonts. In some previous methods, they used two encoders, one for content, the other for style, but their disentanglement of content and style is not sufficiently effective in generating arbitrary fonts. Arbitrary font generation is a challenging task because learning text and font design separately from given font images is very difficult, where the font images have both text content and font style in each image. In this paper, we propose a new automatic font generation method to solve this disentanglement problem. First, we use two stacked inputs, i.e., images with the same text but different font style as content input and images with the same font style but different text as style input. Second, we propose new consistency losses that force any combination of encoded features of the stacked inputs to have the same values. In our experiments, we proved that our method can extract consistent features of text contents and font styles by separating content and style encoders and this works well for generating unseen font design from a small number of reference font images that are human-designed. Comparing to the previous methods, the font designs generated with our method showed better quality both qualitatively and quantitatively than those with the previous methods for Korean, Chinese, and English characters. e.g., 17.84 lower FID in unseen font compared to other methods.11Ysciescopu

Design Strategy of 20nm node single PRAM cell based on TCAD Simulation

Design Strategy of 20nm node single PRAM cell based on TCAD Simulation2