Improving the power-delay performance in subthreshold source-coupled logic circuits

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18$\mu$m CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated

Application of a risk-management framework for integration of stromal tumor-infiltrating lymphocytes in clinical trials

Stromal tumor-infiltrating lymphocytes (sTILs) are a potential predictive biomarker for immunotherapy response in metastatic triple-negative breast cancer (TNBC). To incorporate sTILs into clinical trials and diagnostics, reliable assessment is essential. In this review, we propose a new concept, namely the implementation of a risk-management framework that enables the use of sTILs as a stratification factor in clinical trials. We present the design of a biomarker risk-mitigation workflow that can be applied to any biomarker incorporation in clinical trials. We demonstrate the implementation of this concept using sTILs as an integral biomarker in a single-center phase II immunotherapy trial for metastatic TNBC (TONIC trial, NCT02499367), using this workflow to mitigate risks of suboptimal inclusion of sTILs in this specific trial. In this review, we demonstrate that a web-based scoring platform can mitigate potential risk factors when including sTILs in clinical trials, and we argue that this framework can be applied for any future biomarker-driven clinical trial setting

Disruption to control network function correlates with altered dynamic connectivity in the wider autism spectrum

Autism is a common developmental condition with a wide, variable range of co-occurring neuropsychiatric symptoms. Contrasting with most extant studies, we explored whole-brain functional organization at multiple levels simultaneously in a large subject group reflecting autism's clinical diversity, and present the first network-based analysis of transient brain states, or dynamic connectivity, in autism. Disruption to inter-network and inter-system connectivity, rather than within individual networks, predominated. We identified coupling disruption in the anterior-posterior default mode axis, and among specific control networks specialized for task start cues and the maintenance of domain-independent task positive status, specifically between the right fronto-parietal and cingulo-opercular networks and default mode network subsystems. These appear to propagate downstream in autism, with significantly dampened subject oscillations between brain states, and dynamic connectivity configuration differences. Our account proposes specific motifs that may provide candidates for neuroimaging biomarkers within heterogeneous clinical populations in this diverse condition. Keywords: Autism, Functional MRI, Dynamic connectivity, Control networks, Task-positive, Default-mod

An exploration of mechanisms for dynamic cryptographic instruction set extension

Abstract. Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility. ” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues. Key words: FPGA, embedded processor, instruction set extension.