Extraction of Physical Device Dimensions of Soi Mosfets From Gate Capacitance Measurements

A new technique unique to SOI MOSFETs is presented for extracting the physical device dimensions (effective gate length and gate oxide and film thicknesses) from a set of gate capacitance measurements on transistors with various lengths

A physically-based C-infinity-continuous model for accumulation-mode SOI pMOSFET's

In this paper, we present a unified accumulation-mode (AM) SOI MOSFET model for circuit simulation. The model is valid in all the regimes of normal operation and includes explicit expressions of the drain current and total charges which have an infinite order of continuity; therefore, smooth transitions are assured. Short channel effects have also been accounted for, We have finally proved that our model accurately fits the transistor characteristics for effective channel lengths down to 0.7-mu m

Performances of Soi Cmos Ota Combining Ztc and Gain-boosting Techniques

A folded-cascode CMOS FD SOI OTA with a gain-boosting stage has been designed using the ZTC concept. The measured room-temperature 115dB DC gain for a 113MHz transition frequency outperforms all previous SOI or bulk opamp performances. High-temperature measurements up to 400 degrees C are reported for the first time

Measurement and two-dimensional simulation of thin-film SOI MOSFETs: Intrinsic gate capacitances at elevated temperatures

Intrinsic gate-capacitance characteristics of long-channel SOI MOSFETs are investigated by measurements up to 300 degrees C and by two-dimensional simulations up to 400 degrees C. Room temperature particularities related to impact ionization and floating body are successfully reproduced by a.c. simulations. Transient simulations are used in order to gain a deep physical insight into the observed phenomena. The contribution of majority carriers generated by impact ionization or back accumulation is clearly established. At high temperature, differences with room temperature behavior observed above and below threshold voltage are explained in terms of thermally generated excess carriers and impact ionization reduction. The analyzed features are the threshold voltage, the subthreshold slope, and particular humps near threshold and subthreshold capacitance values. Implications for analog or digital circuit operation are briefly discussed. Copyright (C) 1996 Elsevier Science Lt

Demonstration of the Potential of Accumulation-mode Mos-transistors On Soi Substrates for High-temperature Operation (150-300-degrees-c)

Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300-degrees-C temperature range are reported and discussed. The increases of the threshold voltage shift and off leakage current with temperature of these SOI p-MOSFET's are observed to be much smaller than their bulk equivalents. Simple models are presented to support the experimental data

Fully depleted SOI-CMOS technology for high temperature IC applications

Thin-film fully depleted complementary metal oxide semiconductor (CMOS) silicon-on-insulator (SOI) technology is currentlly considered as the best mature contender for high-temperature analog or mixed-mode IC applications in the 200-400 degrees C temperature range. This is demonstrated by measurement results of the high-temperature performances of several operational transconductance amplifiers (OTA) with increasing architecture complexity. High-temperature design techniques are also proposed and validated by measurements. (C) 1997 Elsevier Science S.A

Fully depleted SOI-CMOS technology for high temperature IC applications

Thin-film fully depleted complementary metal oxide semiconductor (CMOS) silicon-on-insulator (SOI) technology is currentlly considered as the best mature contender for high-temperature analog or mixed-mode IC applications in the 200-400 degrees C temperature range. This is demonstrated by measurement results of the high-temperature performances of several operational transconductance amplifiers (OTA) with increasing architecture complexity. High-temperature design techniques are also proposed and validated by measurements. (C) 1997 Elsevier Science S.A

Improved LOCOS isolation for thin-film SOI MOSFETs

The authors propose the use of a recessed LOCOS technique instead of a standard LOCOS process to eliminate parasitic edge transistor leakage in thin-film SOI MOSFETs. This technique helps to increase the sidewall threshold voltage by both avoiding excess boron segregation into the field oxide, and providing a smoother edge rounding than that obtained by a classical LOCOS process

Design of thin-film fully-depleted SOI CMOS analog circuits significantly outperforming bulk implementations

Although the reduction of parasitic capacitance and the feasibility of diffusion resistors and capacitors free of junction effects have long been recognized as advantages for the realization of analog circuits on SOI substrates, few SOI analog circuits have been reported mainly because the kink effect severely degrades the output characteristics of thick-film SOI MOSFETs and thereby the performances of analog circuits. Operational amplifier solutions such as the use of body contacts, twin-gate devices or gain-boosting have been proposed but offer little improvement over bulk CMOS counterparts, with the exception of the resistance to elevated temperatures. In the present paper we propose new design models and techniques which, by exploiting the smaller subthreshold swing and body factor of thin-film fully-depleted (FD) SOI MOSFETs, could provide a major breakthrough in order to boost the performances of SOI CMOS analog circuits substantially over bulk implementations, especially in the field of low-voltage low-power application