Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design

OV-CDMA System: Concept and Implementation

A new method is proposed to achieve a multirate overlapped code division multiple access system (OV-CDMA) based on a novel code overlapping procedure. The signal-to-interference ratio (SIR) performance has been investigated for such system. A channel model that allows multirate overlapped transmission is presented based on which a closed form solution for the SIR has been derived. In addition, a simple yet very efficient block diagram of the transmitter and the receiver architecture has been proposed for such a system. Based on the proposed block diagram, the encoder-decoder has been implemented using an FPGA. Numerical results show that the newly proposed OV-CDMA scheme outperforms the classical variable processing gain fast frequency hopping CDMA (VPG-FFH-CDMA) for different system scenarios. Finally, real-time measurements have been successfully obtained using a hardware prototype utilizing the simple Xilinx Spartan IIE (XC2S200E) FPGA

Constant Time Hardware Architecture for a Gaussian Smoothing Filter

International audienceIn this paper a new and highly efficient hardware architecture for a bit-serial implementation of a 33 filter on FPGA is developed and presented. The concept is implemented on a Gaussian blur spatial filter and it can be extended to other filters with similar characteristics. The proposed Single Instruction Multiple Data (SIMD) architecture provides a constant operating time independent of the size of the given image while the arithmetic operations are limited to the operations of addition. The Multiple Instruction Multiple Data (MIMD) performance is achieved in a near fraction of the cost. Thus, the hardware's utilization is optimized. The total time needed to perform the filter of interest on the given image is solely dependent on the working clock frequency. The proposed design is evaluated using a small image and is implemented on two FPGA families with various sizes of an image. Also, it is compared with other architectures

A Survey on Fault Injection Techniques

Abstract: Fault tolerant circuits are currently required in several major application sectors. Besides and in complement to other possible approaches such as proving or analytical modeling whose applicability and accuracy are significantly restricted in the case of complex fault tolerant systems, fault-injection has been recognized to be particularly attractive and valuable. Fault injection provides a method of assessing the dependability of a system under test. It involves inserting faults into a system and monitoring the system to determine its behavior in response to a fault. Several fault injection techniques have been proposed and practically experimented. They can be grouped into hardware-based fault injection, software-based fault injection, simulation-based fault injection, emulation-based fault injection and hybrid fault injection. This paper presents a survey on fault injection techniques with comparison of the different injection techniques and an overview on the different tools

A Self Referencing Technique for the RC-pLMS Adaptive Beamformer and Its Hardware Implementation

International audienceIn this paper, we propose a self referencing scheme for the reduced complexity parallel least mean square (RC-pLMS) adaptive beamforming algorithm as means of robustness against possible interruptions in the reference signal and its hardware implementation. The RC-pLMS is a single stage, non-blind, least mean square (LMS) algorithm with modified input vectors formed as a linear combination of the current and the previous input sample. In this context, its convergence and its stability are critically dependent on the availability of its reference signal and are known to severally degrade when discontinued. Thus, for robustness against the pre-mentioned and with respect to the RC-pLMS accelerated convergence and low residual error profile, we propose the use of it’s filtered output, as an alternative learning sequence, whenever the original reference signal is discontinued, i.e. self-referencing. The proposed self referencing approach is evaluated in infinite and finite precision modes on software and on hardware, i.e. Field Programmable Gate Array (FPGA), respectively. Hardware and software simulation validates the RC-pLMS robustness against different reference signal obstruction scenarios, through the use of the proposed self-referencing approach, while maintaining an accelerated convergence behavior, a low complexity architecture and a high precision beam pointing accuracy

Two Stages Parallel LMS Structure: A Pipelined Hardware Architecture

International audienceModern wireless communication systems have tighten the requirements of adaptive beamformers when implemented on Field Programmable Gate Array (FPGA). The set requirements imposed additional constraints such as designing a high throughput, low complexity system with fast convergence and low steady state error. Recently, a parallel multi-stage least mean square (pLMS) structure is proposed to mitigate the listed constraints. pLMS is a two stages least mean square (LMS) operating in parallel and connected by an error feedback. To form the total pLMS error, the second LMS stage (LMS2) error is delayed by one sample and fed-back to combine with that of the first LMS stage (LMS1). pLMS provides accelerated convergence while maintaining minimal steady state error and a computational complexity of order O(N), where N represent the number of antenna elements. However, pipelining the pLMS structure is still difficult due to the LMS coefficient update loop. Thus, in this paper, we propose the application of the delay and sum relaxed look ahead technique to design a high throughput pipelined hardware architecture for the pLMS. Hence, the delayed pLMS (DpLMS) is obtained. Simulation and synthesis result, highlight the superior performance of the DpLMS in presenting a high throughput architecture while preserving accelerated convergence, low steady state error and low computational complexity. DpLMS operates at a maximum frequency of 208.33 MHz and is obtained at the cost of a marginal increase in resource requirements, i.e. additional delay registers compared to the original pLMS design

A Pipelined Reduced Complexity Two-Stages Parallel LMS Structure for Adaptive Beamforming

International audienceIn this paper, we propose a reduced complexity parallel least mean square structure (RC-pLMS) for adaptive beamforming and its pipelined hardware implementation. RC-pLMS is formed by two least mean square (LMS) stages operating in parallel (pLMS), where the overall error signal is derived as a combination of individual stage errors. The pLMS is further simplified to remove the second independent set of weights resulting in a reduced complexity pLMS (RC-pLMS) design. In order to obtain a pipelined hardware architecture of our proposed RC-pLMS algorithm, we applied the delay and sum relaxation technique (DRC-pLMS). Convergence, stability and quantization effect analysis are performed to determine the upper bound of the step size and assess the behavior of the system. Computer simulations demonstrate the outstanding performance of the proposed RC-pLMS in providing accelerated convergence and reduced error floor while preserving a LMS identical O(N) complexity, for an antenna array of N elements. Synthesis and implementation results show that the proposed design achieves a significant increase in the maximum operating frequency over other variants with minimal resource usage. Additionally, the resulting beam radiation pattern show that the finite precision DRC-pLMS implementation presents similar behavior of the infinite precision theoretical results