4 research outputs found

    Electrical Properties of Al/p-Si Structures with Colchicine Organic Thin Film

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    In this study, we have fabricated an Al/Colchicine/p-Si structure and have investigated its current– voltage (I–V) and capacitance–voltage (C–V) characteristics at room temperature. The barrier height and ideality factor values of 0.68 eV and 3.22, respectively, have been obtained from the I-V plot. The value of the barrier height was compared with the barrier height value of 0.50 eV of a conventional Al/p-Si diode. This was attributed to the Colchicine organic film modifying the effective barrier height by affecting the space charge region of the inorganic Si semiconductor substrate. By using C – 2-V characteristics the diffusion potential value has been extracted as 1.32 V. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/3514

    Electrical properties of safranine T/p-Si organic/inorganic semiconductor devices

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    We investigated the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of identically prepared safranine T/p-Si organic/inorganic Schottky devices (total 26 diodes) formed by evaporation of organic compound solution on p-Si semiconductor substrate. It was seen that the safranine T organic thin film on the p-Si substrate showed a good rectifying behavior. The barrier heights and ideality factors of all devices were extracted from the electrical characteristics. The mean barrier height and mean ideality factor from I-V measurements were calculated as 0.59±0.02 eV and 1.80±0.20, respectively. Also, the mean barrier height and mean acceptor doping concentration from C-V measurements were calculated as 0.67±0.10 eV and (6.96±0.37)×1014 cm-3, respectively. The discrepancy in the barrier height values obtained from I-V and C-V characteristics has been attributed to different nature of the measurements. The discrepancy between these values can also be due to the existence of the interfacial native oxide and the organic safranine T thin layer between the semiconductor substrate and top contact metal
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