CAR LICENSE PLATE RECOGNITION BY USING TEMPLATE MATCHING ALGORITHM

Car License Plate Recognition (CLPR) system is one of the important areas in the intelligent traffic engineering field. CLPR is developed to recognize the car license plate with the implementation of Digital Image Processing (DIP) and Template Matching Algorithm (TMA) approaches by using the MATLAB software. This research works on the offline input images collected by using digital camera. The method of this project is based on template matching where a character is identified by analyzing its shape. Then, the current input character is compared to each template to find either an exact match, or the template with the closest representation of the input character. Experimental results show a high accuracy of the developed CLPR on hundreds random sample images of car license plate in Sarawak

Wireless network on-chips history-based traffic prediction for token flow control and allocation

Wireless network-on-chip (WiNoC) uses a wireless backbone on top of the traditional wired-based NoC which demonstrated high scalability. WiNoC introduces long-range single-hop link connecting distanced core and high bandwidth radio frequency interconnects that reduces multi-hop communication in conventional wired-based NoC. However, to ensure full benefits of WiNoC technology, there is a need for fair and efficient Medium Access Control (MAC) mechanism to enhance communication in the wireless Network-on-Chip. To adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs), to ensure efficient utilization of the wireless medium in a WiNoC. This work presents a prediction model that improves MAC mechanism to predict the traffic demand of the WIs and respond accordingly by adjusting transmission slots of the WIs. This research aims to reduce token waiting time and inefficient decision making for radio hub-to-hub communication and congestion-aware routing in WiNoC to enhance end to end latency. Through system level simulation, we will show that the dynamic MAC using an History-based prediction mechanism can significantly improve the performance of a WiNoC in terms of latency and network throughput compared to the state-of-the-art dynamic MAC mechanisms

On the Impact of Routing and Network Size for Wireless Network-on-Chip Performance

Wireless Network-on-Chip or WiNoC is an alternative to traditional planar on-chip networks. On-chip wireless links are utilized to reduce latency between distant nodes due to its capability to communicate with far-away node within a single hop. This paper analyzes the impact of various routing schemes and the effect of WiNoC sizes on network traffic distributions compared to conventional mesh NoC. Radio hubs (4×4) are evenly placed on WiNoC to analyze global average delay, throughput, energy consumption and wireless utilization. For validation, three various network sizes (8×8, 16×16 and 32×32) of mesh NoC and WiNoC architectures are simulated on cycle-accurate Noxim simulator under numerous traffic load distributions. Simulation results show that WiNoC architecture with the 16×16 network size has better average speedup (∼1.2×) and improved network throughputs by 6.36% in non-uniform transpose traffic distribution. However, as the trade-off, WiNoC requires 63% higher energy consumption compared to the classical wired NoC mesh

Using Fixed Column Primer for Computation of Boolean Matrix Multiplication with DNA

In our previous work, we implemented an in vitro implementation of Boolean matrix multiplication with DNA computing. However, with the increase in the problem size, the material consumption of DNA and the number of experimental steps required to compute the problem increases drastically. Thus in this paper, we introduce fixed column primer method to reduce the material consumption and the labour intensiveness of the computation

Markov Chain Modeling for Router Hotspots on Network-On-Chip

A Network-on-Chip (NoC) is a current paradigm in complicated System-on-Chip (SoC) designs that renders compe- tent on-chip communication architecture. It proposes scalable communication to SoC and grants decoupling of communi- cation and computation. In NoC, design space exploration is vital merited to trade-offs among latency, area, and power consumption. Therefore, analytic modeling is crucial step for early NoC design. This paper delivers a top-down approach router model, and employs this model for mesh NoC performance analysis quantified in terms of throughput, average of queue size, efficiency, loss and waiting time. As a case study, the advised model is applied to map a MPEG4 video core to a 4 × 4 mesh NoC with deterministic routing to evaluate the overall NoC quality of service (QoS). The model is utilized as well to acquaints how much occupancy of average queue size for each router that reduces resources (hardware) area and cost. The accuracy of our approach and its practical use is illustrated through extensive simulation results

Performance Analysis in Mesh Network-on-Chip Topology by using Multilevel Network Partitioning

The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of the performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application with four famous partitioning algorithms (Linear, Spectral, Tailor-Made and Kerninghan-Lin). Experimental results show that second level of spectral partitioning gives the best performance compared to another network partitioning

Field Programmable Gate Array (FPGA)-based Intelligent Management System for Home Appliances

This project reviews the implementation of FPGA-based system design on common home appliances in order to achieve energy efficient usage on the appliances. There are many existed method on this subject in the real world. One common method is using the Pulse Width Modulation (PWM) to control the motor speed of the home appliances. In this project, an energy saving home automation was designed using the Quartus II software. The design included a security system, curtain controller, lighting controller and a PWM generator. Security system provides protection to the house. Curtain controller and lighting controller were designed to save electricity and at the same time maintain the house in the bright condition. PWM generator was designed to optimize the air-conditioner and thermostat usage and thus save energy. Not only this system has energy saving feature but it also provide security to the users. At the end of this project, the design has successfully implemented and tested using FLEX10k chip on LP2900 board. The real implementation on hardware has not been done yet but theoretically it is proven that the designed system can save electricity

Area Optimization for Networks-on-Chip Architectures using Deep Network Partitioning

This paper presents an area optimization for Network-on-Chip (NoC) architecture using deep Network Par- titioning technique. Among the hardest problems in NoC design is customizing the topological structure and application mapping on on-chip network in order to cater for application demand at minimal cost. The area cost of NoC is cut down by utilizing multi- level network partitioning where it partitions large networks into smaller segments. The enhancement in area cost is obtained by reducing both router area and the number of global links. In terms of performance, the multi-level network partitioning offers a better solution by assigning computational cores with heavy inter-core communications into the same segment. Therefore, the average inter-node distances would be minimized. This directly results in better performance due to its shortest path. For verification, the proposed technique has been tested on various System-on-Chip (SoC) applications case studies. The proposed technique results in the reduction of more than 7% router area, 19% global links, and 12% average inter-node distance

Simulation-Based Power Estimation for High Throughput SHA-256 Design on Unfolding Transformation

In recent years, security has grown in importance as a research topic. Several cryptographic SHA-256 hash algorithms have been developed to enhance the performance of data-protection techniques. In security system designs where data transmission must be properly encrypted to avoid eavesdropping and unwanted monitoring, the Hash Function is vital. In constructing the SHA-256 algorithm, high speed, compact size, and low power consumption are all factors to be taken into account for an efficient implementation. The purpose of this project is to reduce dynamic thermal power dissipation of SHA-256 unfolding transformation. State encoding is a method used in reducing power design strategies that have been proposed to lower the dynamic power dissipation of the algorithm. The algorithms are successfully designed using the Altera Quartus II platform. The ModelSim is used to test how accurate the results of simulations written in Verilog code are and to validate them. This study presents the unfolding transformation with Gray encoding approach to reduce the SHA-256 design's power consumption and increase its throughput. The SHA-256 unfolding transformation reduces the amount of clock cycles required for conventional architecture. In this research, the dynamic power SHA-256 unfolding factor 4 with Gray encoding reduces by 43.4 percent from Binary encoding with high throughput of the design. Therefore, it was suggested that to provide high performance of the embedded security system design, an unfolding transformation with Gray encoding design can be applied to the hash function design. Thus, the performance of the SHA-256 design can be greatly enhanced by changing the state encoding with the high number of unfolding factors. Based on this technology, the Power Analyzer in Altera Quartus II may produce an accurate simulation-based power assessment

Implementation of Verilog HDL in Calculator Design with FPGA Simulation

A calculator is a device that can be found in daily life. This paper proposed the design of a calculator using Verilog HDL. A series of synthesizable Verilog code was created and simulated on Quartus II 15.0. The design of an 8-bit calculator can solve mathematical operations such as addition, subtraction, multiplication, division, square and cube functions, square root and factorial. This calculator consists of eight-digit numbers. In this paper, among the family devices in Altera, Cyclone V was used to perform the simulation process. The outputs are shown in the RTL viewer and waveform simulation of the calculator design. The implementation of a calculator was successfully designed using Verilog HDL in terms of digit numbers and the operation of the calculator function