Radix-2n serial–serial multipliers

All serial–serial multiplication structures previously reported in the literature have been confined to bit serial–serial multipliers. An architecture for digit serial–serial multipliers is presented. A set of designs are derived from the radix-2n design procedure, which was first reported by the authors for the design of bit level pipelined digit serial–parallel structures. One significant aspect of the new designs is that they can be pipelined to the bit level and give the designer the flexibility to obtain the best trade-off between throughput rate and hardware cost by varying the digit size and the number of pipelining levels. Also, an area-efficient digit serial–serial multiplier is proposed which provides a 50% reduction in hardware without degrading the speed performance. This is achieved by exploiting the fact that some cells are idle for most of the multiplication operation. In the new design, the computations of these cells are remapped to other cells, which make them redundant. The new designs have been implemented on the S40BG256 device from the SPARTAN family to prove functionality and assess performance

Bit-level pipelined digit-serial array processors

A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented

Pengaruh Dukungan Sosial, Persepsi Risiko Dan Interaksi Sosialterhadap Kepercayaan Dan Niat Pembelian Konsumen Pada Media S-commerce (Studi Pada Konsumen S-commerce Di Indonesia)

The rapid growth of social media in Indonesia leads the user to a level which the form of a new business plan can be developed that is social commerce. S-commerce is a new evolution in the world of internet commerce utilizing social media as a business platform. This study aimsto analyze the effect of social support, risk perception, and social interaction of trust and s-commerce's consumer purchase intentions in Indonesia. Respondents were 148 Facebook user in Indonesia. Data collection through an electronic questionnaire survey method that has been deployed in social networks facebook. Methods and data analysis technique using Structural Equation Model (SEM) – Partial Least Square (PLS). The results showed that social support has dominant effect on consumer's purchase intentions. These findings provide a new view about consumer's activity in social media and has implication on s-commerce company strategy in Indonesia

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Panel: Fantasy and Realit