Large area application of a corn hazard model

An application test of the crop calendar portion of a corn (maize) stress indicator model developed by the early warning, crop condition assessment component of AgRISTARS was performed over the corn for grain producing regions of the U.S.S.R. during the 1980 crop year using real data. Performance of the crop calendar submodel was favorable; efficiency gains in meteorological data analysis time were on a magnitude of 85 to 90 percent

Behaviour and effects of fluorine in annealed n+ polycrystalline silicon layers on silicon wafers

A comprehensive study is made of the behaviour and effects of fluorine in n+ polysilicon layers. Sheet resistance, TEM and SIMS are used to obtain quantitative data for the breakup of the interfacial oxide, the epitaxial regrowth of the polysilicon and the fluorine and arsenic distributions. The fluorine significantly increases both the initial oxide breakup and the initial polysilicon regrowth. It also produces inclusions in the layer which can affect the subsequent polysilicon regrowth and the arsenic distributions. Three regrowth stages and two regrowth mechanisms are distinguished and interpreted and a value of approximately 6x1011cm2s-1 is deduced for the effective diffusivity of fluorine in polysilicon at 950°C

Effect of an oxide cap layer and fluorine implantation on the metal-induced lateral crystallization of amorphous silicon

In this work, we investigate the effect of oxide cap layer on the metal-induced lateral crystallization (MILC) of amorphous silicon. The MILC is characterized at temperatures in the range 550 to 428°C using Nomarski optical microscopy and Raman spectroscopy. It is shown that better lateral crystallization is obtained when the oxide cap layer is omitted, with the crystallization length increasing by 33% for a 15 hour anneal at 550°C. A smaller increase of about 10% is seen at lower temperatures between 525°C and 475°C and no increase is seen below 450°C. It is also shown that the detrimental effect of the oxide cap layer can be dramatically reduced by giving samples a fluorine implant prior to the MILC anneal. Raman spectroscopy shows that random grain growth is significantly less for unimplanted samples without an oxide cap and also for fluorine implanted samples both with and without an oxide cap. The crystallization length improvement for samples without an oxide cap layer is explained by the elimination of random grain crystallization at the interface between the amorphous silicon and the oxide cap layer

Study of fluorine behaviour in silicon by selective point defect injection

This letter reports a point defect injection study of 185 keV 2.3x1015cm?2 fluorine implanted silicon. After an inert anneal at 1000°C, fluorine peaks are seen at depths of 0.3Rp and Rp and a shoulder between 0.5–0.7Rp. The shallow peak (at 0.3Rp) is significantly smaller under interstitial injection than under both inert and vacancy injection conditions. For a longer anneal under interstitial injection, both the shallow peak and the shoulder are eliminated. These results support earlier work suggesting that the shallow fluorine peak is due to vacancy-fluorine clusters which are responsible for suppression of boron thermal diffusion in silicon. The elimination of the shallow fluorine peak and the shoulder is explained by the annihilation of vacancies in the clusters with injected interstitials

Depletion isolation effect in Vertical MOSFETS during transition from partial to fully depleted operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm

Electrical properties of Al-In-Sn alloys directionally solidified in high and low gravitational fields

The Al-In-Sn alloys were directionally solidified in the NASA KC-135 aircraft which flies a series of parabolas to generate high (high-g) and low (low-g) gravity forces parallel to the longitudinal growth axis. Thus, for a given sample, successive sections can be identified which were solidified in high-g and low-g. Measurements of the electronic properties of the samples reveal that: the resistivity of the low-g sections is larger (about a factor of 10) than that of the high-g sections; the low-g sections behave conductively like a semi-metal, while the high-g sections are essentially metallic; and both high-g and low-g sections are superconducting but the superconducting transition temperature of the low-g sections is 1 K higher than that of the high-g sections

Asymmetric gate induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from ?50 to 200?C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain–body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical (110) pillar sidewalls and the horizontal (100) wafer surface