Characterization of a RISC-V Microcontroller Through Fault Injection

This article reports the results of fault injection on a microcontroller based on the RISC-V (Riscy) architecture. The fault injection approach uses fault simulation based on Modelsim and targets a set of 1000 fault injected per microcontroller block and per benchmarck. The chosen benchmarks are the Dhrystone and CoreMark that may represent generic workloads. The results show certain block are more prone to fault than others, as also confirmed by a vulnerability analysis that correlates the number of observed faults and the rate of access to the blocks

Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility

The study of the effects of neutrons induced errors in Commercial Off The Shelf (COTS) components is becoming increasingly important for terrestrial and avionics applications as their potential impact in terms of reliability and safety could be catastrophic. This paper describes the setup and the experimental analysis of neutron irradiation tests performed at the Rutherford Appleton Laboratories (ISIS) neutron accelerator on the NEMESYS (Neutron Effects on MEmory SYStems) platform, a project which has the goal of studying the effects of atmospheric neutrons on COTS components during the stratospheric flight of a balloon. The results of bit upsets on the COTS SRAM and COTS Camera obtained from the tests are discussed and correlated together with a discussion on the observed system Single Event Functional Interrupts (SEFIs) providing an overall characterization of the targeted COTS components as well as on the setup on NEMESYS