A combined receiver front-end for Bluetooth and HiperLAN/2

A Software Defined Radio is a radio receiver that is reconfigurable by software. This reconfigurability leads to flexibility that can be used to offer more functionality to the user. Also, because common reconfigurable hardware can be used for very diverse radio interfaces, production and logistics can be faster and cheaper. In our Software Defined Radio project we aim at a receiver that is able to receive signals of any contemporary or future radio standard. However, because we need tangible specifications in order to design, we have chosen to implement a combination of two rather different standards: Bluetooth and HiperLAN/2. Both the analogue and the digital/software parts are included in the design. A CMOS integrated wideband analogue front-end containing a low noise amplifier, downconversion mixers and filters has been designed. This front-end\ud is connected to a PCB that contains two analogue-to-digital convertors and a sample rate convertor (SRC). The output of this board is connected to a standard PC through a digital I/O board with PCI bus. Software on this PC performs the demodulation.\ud We conclude that an analog wide-band front-end with a flexible SRC combined with appropriate software on an inherently flexible PC forms a promising architecture for Software Defined Radio

A Software Defined Radio Test-bed for WLAN Front Ends

In our Software Defined Radio (SDR) project we aim at combining two different types of standards, Bluetooth and HiperLAN/2 on one common flexible hardware platform. The HiperLAN/2 hardware is that complex compared to the Bluetooth hardware, that Bluetooth capability may be added to the HiperLAN/2 platform at limited cost. The question is how to do this. In this paper we first describe the radio front-end functions and their implementation. Subsequently the test-bed that will assist us in building the hardware platform is described.We present the method by which we use the HiperLAN/2 front-end for Bluetooth reception purposes Our system consists of three parts: analog signal processing, digital channel selection and digital demodulation. The analog processing function is capable of reception of both standards.The demodulation function and channel selection function are implemented in two separate software programs (one for each standard) that allow the exploration of different design alternatives and the assessment of computational cost of the receiver

ADC Clock Jitter Requirements for Software Radio Receivers

The effective number of bits of an analogue-to-digital converter (ADC) is limited not only by the quantisation step inaccuracy, but also by sampling time uncertainty. According to a commonly used model, timing jitter errors should not introduce a sampling error bigger than 1 quantisation level for full swing input signals at a frequency equal to half the sample rate. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. The paper explores the clock jitter requirements for a software radio application, using a more realistic model found in the literature and taking into account both the power spectrum of the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter is not the limiting factor in the feasibility of software radio receivers

A GPP-based Software-Defined Radio Front-end for WLAN Standards

This paper presents a software-defined radio testbed for the physical layer of wireless LAN standards. All baseband physical layer functions have been successfully mapped on a Pentium 4 processor that performs these functions in real-time. This has been tested in combination with a CMOS integrated wideband analog front-end containing a low noise amplier, downconversion mixers and filters. The testbed consists of both a transmitter and a receiver. The transmitter contains a transmitter PC with a DAC board, an Agilent E4438C generator for upconversion and an antenna. The receiver consists of an antenna, a wideband SDR analog frontend and a receiver PC with an ADC board. On this testbed we have implemented two different types of standards, a continuous-phase-modulation based standard, Bluetooth and an OFDM based standard, HiperLAN/2. However, our testbed can easily be extended to other standards, because the only limitations in our testbed are the maximal channel bandwidth of 20 MHz, the dynamic range of the wideband SDR analog front-end and of course the processing capabilities of the used PC