4H-SiC metal oxide semiconductor devices

PhD ThesisMetal oxide semiconductor (MOS) devices are the most important component in advanced integrated circuits (ICs). The success of Si in CMOS technology is owing to the excellent interface formed between Si and SiO2. However, Si-based electronic devices are not suitable to operate in high power, high frequency and high temperature conditions due to material limitations. 4H-SiC with a wide bandgap, high critical electric field, high thermal conductivity and high saturation drift velocity, is an attractive semiconductor material for extreme conditions. However, high quality oxide-semiconductor interfaces are still a major challenge in 4H-SiC MOS devices. This thesis focuses on interface studies of 4H-SiC MOS devices. The main aim is to produce high quality oxide/4H-SiC interfaces by the introduction of an ultrathin SiO2 layer between deposited oxides and 4H-SiC. Ultrathin SiO2 layers can be grown on 4H-SiC using a low thermal budget technique followed by Al2O3 deposition using ALD. N-type and p-type MOS capacitors were fabricated using a gate oxidation of 600 °C for 3 min, which produced SiO2 of thickness 0.7 nm as estimated using ARXPS. Electrical characterisation demonstrates an interface trap density (Dit) of 4-6 × 1011 cm-2eV-1 at 0.2 eV from the conduction and valence band edges. This represents a reduction in Dit by 1-2 orders of magnitude compared to the devices fabricated at 1150 °C for 180 min in the furnace. Furthermore, field effect channel mobility as high as 125 cm2/V.s and a subthreshold slope of 130 mV/dec were obtained from MOSFETs using similar gate stacks. The mobility of MOSFETs decreases with increasing temperature indicating that the electron conductivity is limited by phonon scattering rather than Coulomb scattering, and proves that Dit at the oxide/4H-SiC has been reduced. The ultrathin layer is believed to be a good interface layer between Al2O3 and 4H-SiC. As the temperature and time of the oxidation process increased, resulting in thicker SiO2, the values of Dit increased for both p-type and n-type MOS capacitors. Ultrathin SiO2 layers were also grown underneath a deposited SiO2 layer by N2O annealing at 1175 °C. From n-type MOS capacitor results, the lowest values of Dit obtained were 1.7 × 1012 cm-2eV-1 at 0.2 eV below the conduction band edge, for gate oxides consisting of 60 nm deposited SiO2 followed by 90 min of N2O annealing. This process produced a SiO2 layer 0.68 nm thick, estimated using the Deal-Grove model. The values of Dit increased as the grown SiO2 thicknesses became thicker or thinner than 0.68 nm. This trend is similar to what ii was found in ultrathin SiO2/Al2O3 gate stacks of MOS capacitors proving that 0.7 nm thick is the best thickness of SiO2 to use for 4H-SiC MOS devices. Electrical measurement up to 300 °C proved that these fabricated MOS devices are able to operate well at high temperature. MOSFETs utilizing ultrathin SiO2/Al2O3 gate stacks could retain their enhancement mode behaviour even at high temperature demonstrating the devices capability to be operated in extreme conditions. Both gate stacks also exhibited a low leakage current and were able to withstand electric fields far above 3 MV/cm, which is needed for actual operating system. The scope of these findings points to solutions for the interface challenges in 4H-SiC MOS devices. A thermally grown SiO2 layer 0.7 nm thick exhibited the lowest Dit values for both gate stacks and also produced high field effect channel mobility in MOSFETs. It is anticipated that this fabrication approach will mitigate the oxide/4H-SiC interface problem and contribute towards the development of improved power electronic devices.Ministry of Education Malaysia (MOHE) and in part by the Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka for financially sponsored my study through SLAI scholarship. Special thanks to Engineering and Physical Sciences Research Council (EPSRC), UK for providing the financial support to carry out this research

Prospects Of Molybdenum Thin Film For Solar Cell Application From AFM Analysis

Molybdenum (Mo) was grown on soda lime glass by the radio frequency (RF) magnetron sputtering deposition method to characterize the prospect feature to be used as solar cell back contact. 10 samples were sputtered with different suitable parameter by varying RF target power, argon gas pressure and growth temperature. Then all the samples were analyzed by atomic force microscopy (AFM) to determine their features and specification. The results include molybdenum thin film characteristics of roughness, grain size and root mean square (RMS) is obtained. From these characterization results the paramount parameter condition is obtained which at 200 °C, 6.6 mTorr and 75 Watt. These optimized results can be used in future work for fabricating of molybdenum as back contact layer for solar cell application. In conclusion, this study has obtained the optimized parameter in term of growth temperature, argon (Ar) gas pressure and radio frequency (RF) power for molybdenum growth on thin films that compatible and can be integrated not only for solar cell application but with wide variety of MEMS/NEMS devices

Compatibility Analysis of Silicon Nitride and Silicon Dioxide on HCI induced LDD MOSFET

Hot-carrier-injection (HCI) is one of important reliability issue under short-channel effect in modern MOSFET devices especially in nano-scaled CMOS technology circuits. The effect of the hot carrier can be reduced by introducing Lightly-Doped-Drain (LDD) structure on the device. The objective of this project is to study the effect of hot carrier in the LDD n-MOSFET. The LDD n-MOSFET is stressed with bias voltage at intervals of stressing time to determine the degradation model in the threshold voltage and drain current. From the parametrical analysis, it shows that the shift in threshold voltage and degradation in the drain current occurred after the MOSFET device is stressed with hot carrier stress test. The rate of threshold voltage shift and degradation of the drain current are dependence to the stressing time applied to the MOSFET device. The hot carrier stress test shows that the device with Si3N4 has smaller voltage shift compared to SiO2 material

Thickness Dependence of The Surface Roughness of Micro Contact Deposited By Dc Magnetron Sputtering Technique

Integrated circuits are tested in final step of IC packaging to verify that required electrical connections are working properly. At present, Pogo Pins are used as electrical connection between IC lead and load board. Pogo pins caused different problems including indentation marks, blur marks, tilting, spring malfunction, high maintenance cost and etc. The present miniaturization trends towards higher performance, smaller and lighter product have resulted in an increasing demand for smaller pitch size and increase the issues of testing process with pogo pins. Pogo pins induced reliability problems when dealing with fine-pitch (< 0.5 mm) packages. New electrical conductive cell was designed in previous works. It was based on microstructures instead of pogo pins and consists of three different parts including polymer, metallic micro contactors and liquid metal. New Model was designed for QFP packages with 0.5 mm pitch size using simulation in previous years. Novel test socket mechanical design and analysis were successfully done by previous study. New models with new materials in different shapes were designed and the best one was achieved

PV-Mini Hydro-Diesel Hybrid System in a Village

Nowadays, renewable energy becomes more demanding because of its advantages which are abundant, untapped and environmental friendly. Due to this fact, it is important to have a lot of research to enhance the performance of the renewable energy system. This paper will discuss on design, analysis and performance for optimizing the system using HOMER software in terms of economical and efficiency. The location for this simulation is at Kampung Chuweh, Pulau Banding, Gerik, Perak, which is Orang Asli village. Solar, mini hydro and generator have been used to simulate the system design. All the data and results are provided in this paper

Low Cost Electro-deposition of Cuprous Oxide P-N Homo-junction Solar Cell

Most of the photovoltaic industry uses wafer of single crystal and poly-crystal silicon as a material of their photovoltaic (PV) modules. However, the cost of these modules is high due to the material and processing cost. Cuprous oxides (Cu2O)have several features that suitable for future photovoltaic applications. Cu2O can be prepared with simple methods at very low cost. Cu2O p-n homojunction solar cell is a device that converts sunlight to electrical energy, consists of two similar materials for its p-n junction, which is Cu2O. The p-type and n-type of Cu2O thin films are then fabricated to produce solar cells. Other layers aluminium and glass substrate coated with indium tin oxide (ITO) need to be added as a contact for electrons movement. In this study, p-type Cu2O, n-type Cu2O and p-n junction are prepared in order to become accustomed for solar cell applications. To achieve the optimum deposition conditions, p-n junction solar cell is prepared by two-steps electrochemical deposition process. The result from x-ray diffraction (XRD) shows that the peak is dominated by CuO (1, 1, 1). P-n junction is in between the p-type and n-type of Cu2O layer. Al has the thickness of 427.5nm. The second and the third layer are p and n –type of Cu2O, which have the thickness of 106.9nm and 92.3nm, respectively. Finally the thickness of ITO layer is 131.1nm. An absorption experiment at AM1 light is performed in order to get the I-V curves, and in fact, to study the electrical solar cells p-n homojunction. Based on I-V curve test, the level of energy conversion of cell is 0.00141% with fill factor, FF 0.94813 which proved that Cu2O p-n homojunction solar cell can be fabricated and produced at very low cost and well function

Deposition of Micro Contact Based Probe Cell for IC Testing by Dc Magnetron Sputtering Technique

This study presents the deposition of micro contact probe cell for IC testing deposited by dc sputtering technique on a glass substrate. Micro contact with thickness of 2800-7000 nm were deposited from Copper target at sputtering power of 125 W in argon ambient at a room temperature on a base layer of copper using mask. Then, the micro contacts were investigated by using profilometer. All the obtained results show the potential viability of the novel test fixture and thus solve the limitatio

Development of User-Centered Smart Child Seat for NCAP Requirements Via IoT Platform

Recently, the 'forgotten baby syndrome' term has become a regular headline in the newspaper. The syndrome is referred to a scenario of a child dying from a heat stroke after being accidentally left in a car. Herein, the Smart Child Seat (SCS) has been designed with a real-time monitoring-based system that consists of temperature, humidity, heart rate, sound, ultrasonic and a carbon monoxide sensor to monitor and measure the condition of the child left inside the car. The system's requirement is designed based on the market survey to provide direction for the optimized SCS system. The system will send the notification via the Blynk IoT application to the parents if there is an abnormal reading from the sensor

Universal Mobility-Field Curves For Electrons In Polysilicon Inversion Layer

This paper reports the studies on the inversion-layer mobility in n-channel Poly-Si TFT’s with 1016cm-3 substrate impurity concentration. The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (Eeff) was examined

Effects of exciton-polariton on Mach-Zehnder interference devices

A new optoelectronic device based on excitonpolariton was studied. In particular a Mach-Zehnder interference device fabricated by using a GaAs quantum well was studied. We simulated the output characteristics of Mach-Zehnder interference device by using a Finite Difference Time Domain (FDTD) method. Then we compared them with the experimental results measured in a low-temperature. After that we obtained the numerical values of electro-optic effect coefficients. Those were as large as 105×10-11 m/V for 4.5 K, while 74×10-11 m/V for 77 K. Therefore this estimation is considerably large, showing 57 (4 K) and 41 (77 K) times larger than conventional KDP crystal. This effect is probably caused by the excitonpolariton effect. Furthermore, we performed a photocurrent experiment to understand the transmitted light phase change characteristics, causing such large electro-optics effect at a comparatively higher temperature. Temperature dependence of photocurrent showed that the absorption edge and exciton peak remained constant up to 77 K, and then shifted to lower energy as the temperature increased. This probably explains how the large electro-optic effect can be obtained at a comparatively high temperature, i.e., 77 K