A sub-100nW Power Supply Unit Embedding Untrimmed Timing and Voltage References for Duty-Cycled µW-Range Load in FDSOI 28nm

International audienceThe paper proposes a power supply unit to efficiently supply always-on or duty-cycled IoT loads which consumes in µW-range. This PS achieves the highest 93% and 99% current efficiencies at average output currents of 1µA and 100µA to date, respectively. This unit includes a voltage reference and oscillator to generate autonomously duty-cycled power delivery operation as low as a 30µs on-period. The overall power supply unit exhibits sub-100nA quiescent current and provides a regulated 0.92V power rail with less than 10% variation against temperature, process and input supply range and without trimming. Fully integrated in FDSOI 28nm, the die area is 0.036mm 2 showing a compact and untrimmed solution to supply small die area IoT node in SoC context without any off-chip components. Keywords-duty-cycled voltage regulator, silicon-based oscillator, voltage reference and micro-power management

Design of fully integrated resonance switched capacitor converters in FDSOI technology

International audienceThe integration of power supplies has the potential to reduce the form factor and cost of electronic systems. The resonance switched capacitor (ReSC) converters show a promising performance as it overcomes the charge-sharing losses in switched capacitor (SC) converters. However, the used inductors need an additional manufacture process. This paper investigates the design of ReSC using an integrated air-core inductors in 28 nm FDSOI technology. Different interleaved topologies are discussed using inductance around 1 nH. The flying and bypass capacitors are implemented using MOM capacitors on-chip. With an inductor quality factor around 6-8 and 1 mm 2 silicon, the ReSC converter shows 30 % lower losses with respect to the SC converter at power density of 0.1 W/mm 2. Although the integrated inductor has a relatively poor quality factor, the fully integrated ReSC converters improve the efficiency of the SC converters. It can be seamlessly implemented in the pre-existing technologies

Challenges for fully-integrated resonant switched capacitor converters in CMOS technologies

International audienceSwitched capacitor (SC) converters inherent losses limit the achievement of high efficiencies at high power densities for on-chip context. Hence, techniques are being investigated to enhance the deficient capacitance energy utilization. The resonant switched capacitor (ReSC) converters showed up as a promising candidate for efficient, dense, granular on-chip power supplies. In this paper, we discuss the design of ReSC converter employing integrated on-chip inductance in CMOS technology. We focus on a 2-phases 2:1 ReSC converter with single inductor. We discuss the practical constraints on using the on-chip air-core inductor and how it is going to affect the area of the converter. Using different inductor implementations, we compare the performance of the ReSC and SC converters of the same area. The results point towards the advantage of ReSC converter over the SC converter in case of using an inductor with relatively small area and negligible contact resistance which could be obtained in the 3D technology

A 2.5μW 0.0067mm 2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V V<inf>DD</inf> range

International audienceAchieving 50% Leakage Reduction in FDSOI 28nm over 0.35-1V VDD Range [Placeholder for Author List] [Placeholder for Affiliations] Worst-case design and post silicon tuning are well-established digital design practices reducing timing violations in presence of process, temperature, aging and voltage variations but they suffer from extra power consumption due to overdesign [1]. Adaptive voltage scaling (AVS) [2] and body bias modulation [1] are well-known strategies to dynamically ensure that the digital core can operate at a targeted frequency, even in the presence of delay degradation due to variations. In a multiple voltage islands context, AVS requires many integrated supply generators such as switched capacitor converters that need to be controlled accurately. Also, for a fine-grain compensation, level shifters are required impacting a lot the circuit performances. As FDSOI technology offers the ability of adjusting the transistor speed through high sensitivity (85mV/VBB) VTH tuning by acting on buried Nwell (NW) and Pwell (PW) voltages, back biasing generators have been investigated [3-5]. However, they require an external controller to reach the optimal Back Bias (BB) voltages (no self-adjustment) [3-4] and [5] has a non-negligible area overhead for sub-mm 2 digital core for a narrow compensation range limited to 0.35-0.45V VDD. We therefore propose a variation-aware BB Compensation unit (BBC) which dynamically self-adjusts the N-and P-MOS transistors BB voltages to maintain the target frequency with low-latency tuning (100µs) across wide ranges of supply voltage (0.35-1V) and temperature (-40-125°C). The very low reported area of 0.0067mm 2 makes it affordable for a small digital core area (0.1-2mm 2). Requiring only a reference frequency signal FTGT, the proposed self-operating BBC exhibits 2.5µW quiescent current without any external component. Compared to worst-case design strategy, BBC brings up to 50% leakage reduction @0.45VDD@120°C and reduces the energy per cycle up to 32% compared to worst case design. Providing a continuous BB voltage adjustment (continuous VTH tuning), the target frequency is maintained within a +3.5% accuracy

An integrated electrical interface for frequency tuning of vibrational energy harvesters

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Electromagnetic Mechanical Energy-Harvester IC with No Off-Chip Component and One Switching Period MPPT Achieving up to 95.9% End-to-End Efficiency and 460% Energy-Extraction Gain

International audienceElectromagnetic vibration energy harvesters (EMHs) can harvest mW-range power from sub-g vibrational environments while having a volume of a few cm 3 , Thus, such EMHs are promising candidates for powering net-zero-power sensor nodes as compared to their electrostatic- or piezoelectric-based counterpars [1], [2], especially in the industrial environments (e.g., harvesting energy from stator of motors or rotating wheels)

A self-powered integrated solution for frequency tuning of piezoelectric energy harvesters

International audienceThis paper presents the integrated design of a tunable interface for wideband energy harvesting, the Short-Circuit Synchronous Electric Charges Extraction (SC-SECE). By tuning both the phase of the energy harvesting event, PhiS , and the angular duration of the short-circuit phase, DeltaPhi, this interface maximizes both the harvested energy while tuning the dynamics of the energy harvester. The proposed ASIC is self-powered, includes a cold start, and only consumes less than 1uW, which is a very small percentage of the harvested energy. It includes as well a low-power (24nw) gradient algorithm which controls the value of (PhiS,DeltaPhi) and tries to maximizes the harvested power for any vibration's frequency and amplitude

LDO-assisted Voltage Selector over 0.5-to-1V VDD range for fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition

International audienceThis paper presents a 95% power-efficient duty-cycled LDO-assisted voltage selector (LAVS) for fine grained spatial and temporal voltage scaling in FDSOI 28nm technology. LAVS enables 200ns/V controlled transitions between three power rails over a 0.5-to-1V range while maintaining the digital activity of the supplied load. During transitions, current and voltage detections are proposed to protect power rails from reverse current. LAVS has a 13% Si area overhead to drive a 0.2mm 2 digital load. Thanks to a 100MHz-bandwidth LDO, which is only enabled during transition to save power consumption, the voltage selector also maintains a smooth voltage transition even if a digital load suddenly changes its activity factor (4mV/mA load transient). LAVS achieves 30pJ energy dissipation per voltage transition which is negligible compared to the power consumed by the digital load ([email protected] 2). This therefore allows a MHz dynamic voltage scaling rate

A 30nA quiescent 80nW-to-14mW power-range shock-optimized SECE-based piezoelectric harvesting interface with 420% harvested-energy improvement

International audiencePiezoelectric Energy Harvesters (PEH) are usually used to convert mechanical energy (vibration, shocks) into electrical energy, in order to supply energy-autonomous sensor nodes in industrial, biomedical or domotic applications. Non-linear extraction strategies such as Synchronous Electrical Charge Extraction (SECE) [1-2], energy investing [3] or Synchronized Switch Harvesting on Inductor (SSHI) [4] have been developed to maximize the extracted energy from harmonic excitations. However, in most of today's applications, vibrations are not periodic and mechanical shocks occur at unpredictable rates [4]. SSHI interfaces naturally seemed to be the most appropriate candidate for harvesting shocks as they exhibit outstanding performance in periodic excitations [4]. However, the SSHI strategy presents inherent weaknesses while harvesting shocks, since the invested energy stored in the piezoelectric capacitance cannot be recovered. In this work, we propose a self-starting, battery-less, 0.55mm 2 integrated energy harvesting interface based on SECE strategy which has been optimized to work under shock stimulus. Due to the sporadic nature of mechanical shocks which imply long periods of inactivity and brief energy peaks, the interface's average consumption is optimized by minimizing the quiescent power. A dedicated energy saving sequencing has thus been designed, reducing the static current to 30nA and enabling energy to be extracted with only one single 8µJ shock occurring every 100s. Our SECE-based circuit features a shock FoM 1.6x greater than previous SSHI-based interfaces [4]. The proposed system depicted in Fig.1 is made of a negative voltage converter rectifying the PEH output voltage, and a SECE power path controlled by a sequenced circuit. The sequencing is divided in 4 phases and the associated time diagrams are illustrated in Fig.2. During the sleeping mode T1, all blocks except the shock detection (SD) are turned off. During the starting phase, the energy is stored in CASIC through a cold-start path, increasing VASIC. This will progressively turn on the SD. Next, when stress applied to the piezoelectric material leads to an increase in VREC, the SD checks if the electrical energ

A Shock-Optimized SECE Integrated Circuit

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