Analysis of the high-speed polysilicon photodetector in fully standard CMOS technology

A high-performance lateral polysilicon photodiode was designed in standard 0.18 um CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which gure was limited by the measurement equipment. The high intrinsic (physical) bandwidth is due to a short excess carrier lifetime. The external (electrical) bandwidth is also high because of a very small parasitic capacitance (<0.1 pF). This is the best bandwidth performance among all reported diodes designed in a standard CMOS. The quantum efficiency of this poly photodiode is 0.2% due to the very small light sensitive diode volume. The diode active area is limited by a narrow depletion region and its depth by the technology

A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value

A DC-coupled RF Amplifier in CMOS with DC-feedback

A CMOS multistage RF amplifier with DC coupling is presented. A complete optimisation of the various stages is done to maximize the RF gain for a given power budget. To decrease the effects of offsets and tolerances in high gain multistage amplifiers usually (lossy) AC coupling is used. The presented circuit employs DC coupling and DC control circuitry to avoid coupling-induced\ud losses. Compared to existing competing AC-coupled designs the presented one has much more gain at the same power consumption with a lower die area. For the 3-stage design vehicle, with Rsrc = 500Ω and Cout = 400fF, the maximal signal power gain at 4mA supply current is 33dB at 1.9GHz

A High Voltage Swing 1.9 GHz PA in Standard CMOS

A circuit technique for RF power amplifiers that reliably handle voltage peaks well above the nominal supply voltage is presented. To achieve this high-voltage tolerance the circuit implements switched-cascode transistors that yield reliable operation for voltages up to 7V at RF frequencies in a 2.5V CMOS process. Advantages of this include the possibility to use higherohmic load resistors. The impact of load resistances with higher ohmic values is two-fold. Firstly the demands on matching networks are loosened which translates into a higher efficiency for the matching network. Secondly the signal currents are lower which decreases the impact of any series resistance. A design of a 1.9 GHz power amplifier using the switched cascode approach was made. Simulations on the extracted layout of a single ended side showed 21 dBm of output power at a 25 ohm load with 21 % PAE. A layout improvement was estimated to result in 22 dBm at 30 % PAE

45° light turning mirrors for hybrid integration of silica optical waveguides and photo-detectors

For hybrid integration of an optical chip with an electronic chip with photo diodes and electronic processing, light must be coupled from the optical chip to the electronic chip. This paper presents a method to fabricate metal-free 45° quasi-total internal reflecting mirrors in optical chips that enable 90° out-of-plane light coupling between flip-chip bonded chips. This method is fully compatible with fabrication of conventional optical chips. The mirrors are created using anisotropic etching of 45° facets in a Si substrate followed by fabrication of optical structures. After removal of the mirror-defining Si structures by isotropic etching, the obtained air-optical structure interface directs the output of the waveguides to out-of-plane photo detectors that are mounted flip-chip on the optical chip. Simulations show a reflection efficiency of 72.3 %, while experimentally 47% was measured on a not fully optimized first batch

An audio FIR-DAC in a BCD process for high power Class-D amplifiers

A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at V/sub dd/ = 5 V and the chip area is 2 mm/sup 2/ including the reference diode that can be shared by more channels

A high-voltage level tolerant transistor circuit

A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) connects to a biasing circuit (8), such as a voltage level shifter, providing a variable biasing level (V1) relative to a voltage level (VH) at the high-voltage level node (3)