In situ UHVEM study of {113}-defect formation in Si nanowires

Results are presented of a study of {113}-defect formation in vertical Si nanowire n-type tunnel field effect transistors with nanowire diameters ranging from 40 to 500 nm. The nanowires are etched into an epitaxial moderately As doped n-type layer grown on a heavily As doped n(+) Si substrate. p(+) contacts on the nanowire are created by epitaxial growth of a heavily B doped layer. Using focused ion beam cutting, samples for irradiation are prepared with different thicknesses so that the nanowires are fully or partially embedded in the sample thickness. {113}-defects are created in situ by 2 MeV e-irradiation in an ultra-high voltage electron microscope between room temperature and 375 degrees C. The observations are discussed in the frame of intrinsic point defect properties, taking into account the role of dopants and capping layers. The important impact of the specimen thickness is elucidated

Hall effect measurements in double-gate SOI MOSFETs

The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around transistors is extracted by Hall effect measurements at room and liquid nitrogen temperature. The Hall mobility is compared with the drift mobility determined from the transconductance measurement of the devices in strong inversion. The results of this study indicate that the method based on I-D/(g(m))(0.5) provides acceptable values for the drift mobility. The experiment reveals high carrier mobility dominated at room temperature by a phonons scattering mechanism and at low temperature by mixed scattering processes, with a predominance of the surface roughness scattering mechanism. No evidence was found for special transport mechanisms induced by volume inversion in relatively thick SOI films. (C) 2001 Elsevier Science Ltd. All rights reserved

Total-dose effects in double-gate-controlled NPN bipolar transistors

The sensitivity to radiation-induced degradation of new double-gate-controlled lateral NPN bipolar transistors has been investigated. The radiation hardness is improved when the device is working in the accumulation mode. The effect of positive charge and increased surface recombination velocity is analyzed by means of device simulations and experimental result

Performance of gamma-irradiated Gate-All-Around SOI MOS OTA amplifiers

Gate-All-Around SOI MOSFETs are very promising for the fabrication of ultra rad-hard circuits. The specific structure of the GAA device allows to combine radiation hardness and the great technological potential of SOI technology, e.g. for low-voltage low-power or high temperature circuits. Up to now only few studies have been realized on rad-hard GAA analog circuits. Present work discusses the performances of GAA SOI Operational Transconductance Amplifier (OTA) implementations under γ-rays irradiation. The main OTA parameters, i.e. DC open-loop gain and gain-bandwidth product, have been investigated and correlated to the evolution of the Early voltage and the scaled transconductance of individual devices. The experiments were performed up to a total dose of 15 Mrad(Si) on two OTA architectures

Edge effects characterization in gate-all-around SOI MOSFETs

The well-known edge effect due to conduction in the parasitic edge transistor at low gate voltages takes place when the threshold voltage is lowered at the device edges. A bump in the subthreshold characteristic then appears, which is detrimental to circuit performance. Several solutions have been proposed for SOI nMOSFETs, including (a) additional heavy dose boron implant at the edges followed by diffusion, and (b) specially designed SOI transistors such as edgeless devices or H-gate MOSFETs. However, these solutions are not applicable to gate-all-around (GAA) transistors due to their particular structure and fabrication process. In GAA devices, the entire active area is surrounded by the gate oxide and the gate electrode, which renders the use of edgeless structures impossible. Moreover, an oxidation step is performed in order to round the transistor edges, and gate oxide is grown all around the Si island. These steps reduce transistor width and preclude the formation of a heavy boron doped diffusion zone at the edges. This paper presents a process solution which can be applied to GAA transistors in order to suppress the edge leakage problem. Simulated and experimental curves are presented, together with edge effect characterization by both I-V and charge pumping measurements. The charge pumping method requires the use of a body contacted device. Such a device has been realized for the GAA structure. The body contact is achieved through contacting the transistor body through the gate material. This can be realized along either one or both sides of the device