The Programmable Logic-in-Memory (PLiM) Computer (Invited)

Realization of logic and storage operations in memristive circuits have opened up a promising research direction of in-memory computing. Elementary digital circuits, e.g., Boolean arithmetic circuits, can be economically realized within memristive circuits with a limited performance overhead as compared to the standard computation paradigms. This paper takes a major step along this direction by proposing a fully-programmable in-memory computing system. In particular, we address, for the first time, the question of controlling the in-memory computation, by proposing a lightweight unit managing the operations performed on a memristive array. Assembly-level programming abstraction is achieved by a natively-implemented majority and complement operator. This platform enables diverse sets of applications to be ported with little effort. As a case study, we present a standardized symmetric-key cipher for lightweight security applications. The detailed system design flow and simulation results with accurate device models are reported validating the approach.LSI

Requirements and Challenges for Modelling Redox-based Memristive Devices

Developing highly accurate and predictive models of redox-based memristive devices is highly important to enable future memory and logic design. As the switching mechanism is not known in all details yet, accurate device modeling is quite challenging. Here, we introduce six evaluation criteria for modeling filamentary switching devices based on the valence change mechanism, which is a subclass of redox-based memristive devices. The criteria include the plausibility of the simulated I-V and I-t characteristics, the nonlinearity of the switching kinetics, the feasibility of predicting complementary resistive switching correctly, the possibility of programming different resistance states, the state-dependence of the resistive switching, and the occurrence of a fading memory behavior. Four different models that have been proposed in literature are analyzed with respect to these criteria. These models are Kvatinsky's VTEAM model, the Stanford RRAM model, Strachan's TaOx memristor model and a nonlinear physics-based model proposed by our group

Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory

Memristive devices can be exploited for memory as well as logic operation paving the way for non von-Neumann Computation-In-Memory architectures. To validate the potential of such architectures accurate compact models for the memristive devices are required. As a standard device is not available, evaluating the performance of such an architecture is ambiguous. This paper proposes a flexible model for bipolar, filamentary switching, redox-based memristive devices. The model does catch both the device resistance ratio as well as the nonlinearity of the switching kinetics. It is used to perform design exploration for three memristive based circuit design (IMPLY, MAGIC and CRS) for computation-in-memory architectures

Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays

Low operating voltage, high storage density, non-volatile storage capabilities, and relative low access latencies have popularized memristive devices as storage devices. Memristors can be ideally used for in-memory computing in the form of hybrid CMOS nano-crossbar arrays. In-memory serial adders have been theoretically and experimentally proven for crossbar arrays. To harness the parallelism of memristive arrays, parallel-prefix adders can be effective. In this work, a novel mapping scheme for in-memory Kogge-Stone adder has been presented. The number of cycles increases logarithmically with the bit width N of the operands, i.e., O(log2N), and the device count is 5N. We verify the correctness of the proposed scheme by means of TaO× device model-based memristive simulations. We compare the proposed scheme with other proposed schemes in terms of number of cycle and number of device

Sklansky tree adder realization in 1S1R resistive switching memory architecture

Redox-based resistive switches are an emerging class of non-volatile memory and logic devices. Especially, ultimately scaled transistor-less passive crossbar arrays using a selector/resistive-switch (1S1R) configuration are one of the most promising architectures. Due to the scalability and the inherent logic and memory capabilities of these devices, they are good candidates for logic-in-memory approaches. But due to the memory architecture, true parallelism can only be achieved by either working on several arrays at the same time or at multiple lines in an array at the same time. In this work, a Sklansky tree adder is presented, which exploits the parallelism of a single crossbar array. The functionality is proven by means of memristive simulations using a physics-based TaOx model. The circuit and device requirements for this approach are discussed