Graphics-processing-unit-based acceleration of electromagnetic transients simulation.

This paper presents a novel parallelization approach to speedup EMT simulation, using GPU-based computing. This paper extends earlier published works in the area, by exploiting additional parallelism to accelerate EMT simulation. A 2D-parallel matrix-vector multiplication is used that is faster than previous 1D-methods. Also this paper implements a simpler GPU-specific sparsity technique to further speed up the simulations as available CPU-based sparse techniques are not suitable for GPUs. Additionally, as an extension to previous works, this paper demonstrates modelling of a power electronic subsystem. A low granularity system, i.e. one with a large cluster of busses connected to others with a few transmission lines is considered, as is also a high granularity where a small cluster of busses is connected to other clusters thereby requiring more interconnecting transmission lines. Computation times for GPU-based computing are compared with the computation times for sequential implementations on the CPU. The paper shows two surprising differences of GPU simulation in comparison with CPU simulation. Firstly, the inclusion of sparsity only makes minor reductions in the GPU-based simulation time. Secondly excessive granularity, even though it appears to increase the number of parallel computable subsystems, significantly slows down the GPU-based simulation

Simulation-based optimisation of LCC-HVDC controller parameters using surrogate model solvers

This paper proposes the use of surrogate model optimisation methods to solve box constrained LCC-HVDC controller tuning problems. The tuning problem is the selection of the proportional-integral controller gains and voltage-dependant current order limiter parameters of an LCC-HVDC link subject to two operational scenarios and a set of large-signal disturbances. The solvers using recently proposed surrogate model methods performed either similarly to or significantly better than solvers using mature methods of the types found in PSCAD/EMTDC, thus confirming the suitability of these surrogate model solvers for simulation-based optimisation of LCC-HVDC controllers

FPGA implementation of impedance-compensated phase-locked loop for HVDC converters

The phase-locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance-compensated phase-locked loop (IC-PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the phase locking more robust against transients and harmonics. The IC-PLL has an improved dynamic response as compared with the traditional approaches. However, earlier studies on the IC-PLL are mainly based on off-line simulations. In this study, an actual IC-PLL is constructed in hardware and its performance is investigated by connecting it to a real-time model of a line-commutated converter-based HVDC system on a real-time digital simulator. The proposed IC-PLL is constructed using a field-programmable gate array platform. Paralleled and pipelined structures are implemented on the FPGA to achieve low latency and high speed. The performance of the IC-PLL is tested by exposing it to different type of system disturbances such as sudden step change in power, voltage magnitude change and voltage distortion. Results are compared with the traditional trans-vector PLL. The results show the performance of the IC-PLL is superior

A Selective Fault Clearing Scheme for a Hybrid VSC-LCC Multi-Terminal HVdc System

A selective fault clearing scheme is proposed for a hybrid voltage source converter (VSC)-line commutated converter (LCC) multi-terminal high voltage direct current (HVdc) transmission structure in which two small capacity VSC stations tap into the main transmission line of a high capacity LCC-HVdc link. The use of dc circuit breakers (dc CBs) on the branches connecting to VSCs at the tapping points is explored to minimize the impact of tapping on the reliability of the main LCC link. This arrangement allows clearing of temporary faults on the main LCC line as usual by force retardation of the LCC rectifier. The faults on the branches connecting to VSC stations can be cleared by blocking insulated gate bipolar transistors (IGBTs) and opening ac circuit breakers (ac CB), without affecting the main line’s performance. A local voltage and current measurement based fault discrimination scheme is developed to identify the faulted sections and pole(s), and trigger appropriate fault recovery functions. This fault discrimination scheme is capable of detecting and discriminating short circuits and high resistances faults in any branch well before 2 ms. For the test grid considered, 6 kA, 2 ms dc CBs can easily facilitate the intended fault clearing functions and maintain the power transfer through healthy pole during single-pole faults