Nutritional status in under five children and their associated risk factors in an urban slum of Mumbai

Background: Young children living in urban slums are at high risk for acute malnutrition and stunting. Many factors contribute towards it including living conditions, gender, delivery method, or access to nutrition. Malnutrition at a young age can cause morbidity and mortality, and impact further development and educational outcomes of children, and cause lifelong impairment. The aim of this study was to assess the nutritional status of young children in an urban slum in Mumbai and the factors affecting the health of children.Methods: A community based cross sectional study was conducted in the slum community of Dharavi, Mumbai. Data was collected using pre-designed and pre-tested proforma by interview method.Results: The prevalence of wasting (W/H) was found in 48.9% of the population in this study, of which 25.0% had severe acute malnutrition (SAM) and 23.9% had moderate acute malnutrition (MAM). Stunting was found in 39.7% of the population, of which 29.5% were moderately stunted and 10.2% were severely stunted. Wasting was found to be highly correlated with the age of the child and the age of the mother, whereas Stunting was found to be highly correlated with the child, the age of the mother, and complementary feeding.Conclusions: Poor nutritional status of children in the urban slums in Mumbai needs to be addressed by improving education and awareness amid parents and access to Anganwadi, Balwadi, and nutritional supplements.

INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search

Logic synthesis is the first and most vital step in chip design. This steps converts a chip specification written in a hardware description language (such as Verilog) into an optimized implementation using Boolean logic gates. State-of-the-art logic synthesis algorithms have a large number of logic minimization heuristics, typically applied sequentially based on human experience and intuition. The choice of the order greatly impacts the quality (e.g., area and delay) of the synthesized circuit. In this paper, we propose INVICTUS, a model-based offline reinforcement learning (RL) solution that automatically generates a sequence of logic minimization heuristics ("synthesis recipe") based on a training dataset of previously seen designs. A key challenge is that new designs can range from being very similar to past designs (e.g., adders and multipliers) to being completely novel (e.g., new processor instructions). %Compared to prior work, INVICTUS is the first solution that uses a mix of RL and search methods joint with an online out-of-distribution detector to generate synthesis recipes over a wide range of benchmarks. Our results demonstrate significant improvement in area-delay product (ADP) of synthesized circuits with up to 30\% improvement over state-of-the-art techniques. Moreover, INVICTUS achieves up to $6.3\times$ runtime reduction (iso-ADP) compared to the state-of-the-art.Comment: 20 pages, 8 figures and 15 table

ASSURE: RTL Locking Against an Untrusted Foundry

Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (IC) and fabricate them in a third-party foundry. Unauthorized IC copies cost these companies billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after the synthesis tools embed the semantic information into the netlist. We propose ASSURE to protect hardware IP modules operating on the register-transfer level (RTL) description. The RTL approach has three advantages: (i) it allows designers to obfuscate IP cores generated with many different methods (e.g., hardware generators, high-level synthesis tools, and pre-existing IPs). (ii) it obfuscates the semantics of an IC before logic synthesis; (iii) it does not require modifications to EDA flows. We perform a cost and security assessment of ASSURE.Comment: Submitted to IEEE Transactions on VLSI Systems on 11-Oct-2020, 28-Jan-202