Module Relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

International audienceHeterogeneous Reconfigurable Systems-on-Chip (HRSoC) contain as their name suggests, heterogeneous processing elements in a single chip. Namely, several processors, hardware accelerators as well as communication networks between all these components. In order to leverage the programming complexity of this kind of platform, applications are described with software threads, running on processors, and hardware threads, running on FPGA partitions. Combining techniques such as dynamic and partial reconfiguration and partial readback with the knowledge of the bitstream structure offer the ability to target several partitions using a unique configuration file. Such a feature permits to save critical memory resources. In this article, we propose to tackle the issue of designing fully independent partitions, and especially to avoid the routing conflicts which can occur when using the standard Xilinx FPGA design flow. To achieve the relocation process successfully, we propose a new design flow dedicated to the module relocation, using the standard tools and based on the Isolation Design Flow (IDF), a special flow provided by Xilinx for secure FPGA applications

HW-SW Real-Time Operating system for AC drive applications

International audienc

On-line real-time scheduling of multiple version material tasks on FPGA

Ce papier s'inscrit dans la problématique de conception des RSoC (Reconfigurable System-On-a-Chip) disposant d'un système d'exploitation temps réel (RTOS). Nous étudions l'ordonnancement et le placement en ligne des tâches matérielles multi-versions sur FPGA partiellement reconfigurable. En effet, une tâche matériellle peut être synthetisée en plus d'une version et avoir plusieurs tailles et/ou formes avec les caractéristiques temporelles conséquentes. Nous évaluons l'apport de cette approche à tâches multi-versions sur quelques algorithmes d'ordonnancement dans un contexte en ligne. A travers des métriques pertinentes (taux de réjection des tâches, taux d'occupation, makespan), les résultats montrent que cette approche améliore significativement l'ordonnancement sans modifier sa complexité algorithmique. Par exemple, pour les tâches de classe de laxité B ayant 2 versions, le taux de rejection des tâches est diminué de 46\% pour un temps d'exécution moyen de l'algorithme d'ordonnancement inchangé en comparaison à l'algorithme EDF (Earliest Deadline First) utilisant des tâches mono-version

Exploring RTOS issues with a high-level model of a reconfigurable

SoC platfor

Reliability assessment of backward error recovery for SRAM-based FPGAs

International audienceno abstrac

Design and validation methodology of FPGA-based motor drive for High Temperature environment

International audienceThis paper presents a scalable design and verification methodology for FPGA-based motor drives for aircraft application, working at high-temperature environment. ProASICPlus from Actel Family (0.22 μm digital CMOS 4 Layer Metal Flash-Based CMOS Process) was chosen to implement the studied motor drive which consists on a current control. The design is implemented at a frequency of 24 MHz and junction temperature above 125°C. The die is supplied with 2.25v. The proposed methodology is based on similar ASIC design verification including synthesis, place and route, timing analysis steps for each control block. As entire system verification, a Real-Time Simulation (RTS) of the electrical systems is used to guarantee the proof of the motor drive functionality under several operating conditions. Co-simulation results are provided in order to prop up efficiency and interest of the proposed methodology in such application

SoPC-based current controler for Permanent Magnet Synchronous Machines drive

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Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead

International audienceno abstrac

Optimal hardware/software partitioning of asystem on chip FPGA-based sensorless AC drive current controller

International audienceThe recent field programmable gate array (FPGA) system on chip devices offer a new degree of design freedom. Indeed, these digital components allow the combination of software treatment (by the on-chip processor cores) and hardware treatment (hardware architecture made by the interconnection of the FPGA logic cells). In the field of industrial control applications, this digital technology is appropriate to reach an optimum between the control performances, the controller algorithm complexity and the design flexibility. On the other hand, a co-design methodology is necessary to make an efficient partitioning of the control algorithm so as to define modules to be software-made and modules to be hardware-made. To this aim, this paper deals with a co-design methodology adapted to SoC FPGA-based controllers for embedded power applications. The case study is a sensorless current controller of a synchronous machine using an extended Kalman filter (EKF). This co-design development is based on two reference implementations: a full software implementation and a full hardware implementation that are also discussed. To find the optimal HW/SW partitioning, a non-dominated sorting genetic algorithm (NSGA-II) is used