High-Performance and Energy Efficient Multi-Band I/O Interface for 3D Stacked Memory

This dissertation describes the development of an energy efficient 3D multi-band I/O interface to meet the demand for high computation and improve battery life for future mobile memory interface exploiting 3D integration. The multi-band I/O (MBI) interface utilizes 3D integration, amplitude shift keying modulation/demodulation scheme for two radio frequency (RF) band transceivers, and CMOS driver with resistive feedback for the baseband (BB) transceiver. It enables transceiving three bands simultaneously that results in significant enhancements in energy efficiency and aggregate bandwidth. The 3D MBI system was implemented in 130nm CMOS process technology. It obtains a high aggregate data rate of 14.4Gb/s and an energy efficiency of 2.6pJ/b compared with prior works

ELECTRONIC MARKETING FOR FINANCIAL SERVICES: A CASE STUDY ON ISLAMIC BANKS IN THE UNITED ARAB EMIRATES

E-marketing widely facilitated the banking sector as it enabled financial institutions to enhance their servicesand access global arenas. To further validate this, the current study intends to identify the extent to whichIslamic banks in the UAE employ e-marketing and its role in enhancing the relationship with customers andits influence on the quality of banking services. The researchers also seek to provide pertinent information tohelp bank departments to adapt and integrate e-marketing in Islamic services. For data gathering purposes, n=12 questionnaires were distributed among the services sector employees in Dubai Islamic Bank and SharjahIslamic Bank. Results revealed that there is a significant relationship between the adaptation of e-marketingand the improved quality of banking services. Additionally, the results also indicated statistically significantdifferences in the responses regarding the banking services due to the varying demographic factors of thepotential clients. Thus, the researchers recommend that the awareness and adoption of e-marketing throughemployee training can be of greater pre-eminence. Especially in Islamic banking, relying on contemporarymarketing technology can play a sturdy role to improve their services and sustain better relations with thecustomers

High-Performance and Energy Efficient Multi-Band I/O Interface for 3D Stacked Memory

This dissertation describes the development of an energy efficient 3D multi-band I/O interface to meet the demand for high computation and improve battery life for future mobile memory interface exploiting 3D integration. The multi-band I/O (MBI) interface utilizes 3D integration, amplitude shift keying modulation/demodulation scheme for two radio frequency (RF) band transceivers, and CMOS driver with resistive feedback for the baseband (BB) transceiver. It enables transceiving three bands simultaneously that results in significant enhancements in energy efficiency and aggregate bandwidth. The 3D MBI system was implemented in 130nm CMOS process technology. It obtains a high aggregate data rate of 14.4Gb/s and an energy efficiency of 2.6pJ/b compared with prior works

A High FoM and Low Phase Noise Edge-Injection-Based Ring Oscillator in 350 nm CMOS for Sub-GHz ADPLL Applications

This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce jitter variations, minimize oscillator spurious signals, and eliminate periodical phase error, a double edge-injection (window injection) scheme with synchronized edge directions is proposed. A combinational edge generator is utilized to substitute the sequential edge generators for injection timing requirements relaxation. By biasing devices in deep triode, digitally controlled delay cells currents are adopted for frequency tuning. This helps reducing the devices flicker (1/f) noise and minimize the DCRO overall phase noise. At 1 MHz offset of frequency, the proposed oscillator has a measured phase noise of −125.95 dBc/Hz and −115.6 dBc/Hz at oscillation frequencies of 913.4 MHz and 432.6 MHz, respectively. Fabricated in 350 nm CMOS process, with a maximum power consumption of 3.3 mW, and oscillating at 913.4 MHz, this DCRO achieves a tuned oscillator figure of merit (FoM) of −197.35 dBc/Hz. The core area of this edge-injection-based DRCO is only 0.08 mm2

Low-Area and Low-Power VLSI Architectures for Long Short-Term Memory Networks

Long short-term memory (LSTM) networks are extensively used in various sequential learning tasks, including speech recognition. Their significance in real-world applications has prompted the demand for cost-effective and power-efficient designs. This paper introduces LSTM architectures based on distributed arithmetic (DA), utilizing circulant and block-circulant matrix-vector multiplications (MVMs) for network compression. The quantized weights-oriented approach for training circulant and block-circulant matrices is considered. By formulating fixed-point circulant/block-circulant MVMs, we explore the impact of kernel size on accuracy. Our DA-based approach employs shared full and partial methods of add-store/store-add followed by a select unit to realize an MVM. It is then coupled with a multi-partial strategy to reduce complexity for larger kernel sizes. Further complexity reduction is achieved by optimizing decoders of multiple select units. Pipelining in add-store enhances speed at the expense of a few pipelined registers. The results of the field-programmable gate array showcase the superiority of our proposed architectures based on the partial store-add method, delivering reductions of 98.71% in DSP slices, 33.59% in slice look-up tables, 13.43% in flip-flops, and 29.76% in power compared to the state-of-the-art.</p