38 research outputs found
Fault-tolerant Quantum Error Correction on Near-term Quantum Processors using Flag and Bridge Qubits
Fault-tolerant (FT) computation by using quantum error correction (QEC) is
essential for realizing large-scale quantum algorithms. Devices are expected to
have enough qubits to demonstrate aspects of fault tolerance in the near
future. However, these near-term quantum processors will only contain a small
amount of noisy qubits and allow limited qubit connectivity. Fault-tolerant
schemes that not only have low qubit overhead but also comply with geometrical
interaction constraints are therefore necessary. In this work, we combine flag
fault tolerance with quantum circuit mapping, to enable an efficient
flag-bridge approach to implement FT QEC on near-term devices. We further show
an example of performing the Steane code error correction on two current
superconducting processors and numerically analyze their performance with
circuit level noise. The simulation results show that the QEC circuits that
measure more stabilisers in parallel have lower logical error rates. We also
observe that the Steane code can outperform the distance-3 surface code using
flag-bridge error correction. In addition, we foresee potential applications of
the flag-bridge approach such as FT computation using lattice surgery and code
deformation techniques.Comment: 11 pages, 14 figures, comments are most welcom
Timing and resource-aware mapping of quantum circuits to superconducting processors
Quantum algorithms need to be compiled to respect the constraints imposed by
quantum processors, which is known as the mapping problem. The mapping
procedure will result in an increase of the number of gates and of the circuit
latency, decreasing the algorithm's success rate. It is crucial to minimize
mapping overhead, especially for Noisy Intermediate-Scale Quantum (NISQ)
processors that have relatively short qubit coherence times and high gate error
rates. Most of prior mapping algorithms have only considered constraints such
as the primitive gate set and qubit connectivity, but the actual gate duration
and the restrictions imposed by the use of shared classical control electronics
have not been taken into account. In this paper, we present a timing and
resource-aware mapper called Qmap to make quantum circuits executable on a
scalable superconducting processor named Surface-17 with the objective of
achieving the shortest circuit latency. In particular, we propose an approach
to formulate the classical control restrictions as resource constraints in a
conventional list scheduler with polynomial complexity. Furthermore, we
implement a routing heuristic to cope with the connectivity limitation. This
router finds a set of movement operations that minimally extends circuit
latency. To analyze the mapping overhead and evaluate the performance of
different mappers, we map 56 quantum benchmarks onto Surface-17. Compared to a
prior mapping strategy that minimizes the number of operations, Qmap can reduce
the latency overhead up to 47.3% and operation overhead up to 28.6%,
respectively.Comment: Include details on the resource-constrained scheduling algorithm.
Comments are most welcom
Interconnect Fabrics for Multi-Core Quantum Processors: A Context Analysis
Quantum computing has revolutionized the field of computer science with its
extraordinary ability to handle classically intractable problems. To realize
its potential, however, quantum computers need to scale to millions of qubits,
a feat that will require addressing fascinating yet extremely challenging
interconnection problems. In this paper, we provide a context analysis of the
nascent quantum computing field from the perspective of communications, with
the aim of encouraging the on-chip networks community to contribute and pave
the way for truly scalable quantum computers in the decades to come.Comment: 6 pages, 4 figures; appearing in Proceedings of the IEEE/ACM NoCArc
202
Mapping quantum algorithms to multi-core quantum computing architectures
Current monolithic quantum computer architectures have limited scalability.
One promising approach for scaling them up is to use a modular or multi-core
architecture, in which different quantum processors (cores) are connected via
quantum and classical links. This new architectural design poses new challenges
such as the expensive inter-core communication. To reduce these movements when
executing a quantum algorithm, an efficient mapping technique is required. In
this paper, a detailed critical discussion of the quantum circuit mapping
problem for multi-core quantum computing architectures is provided. In
addition, we further explore the performance of a mapping method, which is
formulated as a partitioning over time graph problem, by performing an
architectural scalability analysis
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package
The grand challenge of scaling up quantum computers requires a full-stack
architectural standpoint. In this position paper, we will present the vision of
a new generation of scalable quantum computing architectures featuring
distributed quantum cores (Qcores) interconnected via quantum-coherent qubit
state transfer links and orchestrated via an integrated wireless interconnect.Comment: 5 pages, 2 figures, accepted for presentation at the IEEE
International Symposium on Circuits and Systems (ISCAS) 202
Fault-tolerant quantum error correction on near-term quantum processors using flag and bridge qubits
Fault-tolerant (FT) computation by using quantum error correction (QEC) is essential for realizing large-scale quantum algorithms. Devices are expected to have enough qubits to demonstrate aspects of fault tolerance in the near future. However, these near-term quantum processors will only contain a small amount of noisy qubits and allow limited qubit connectivity. Fault-tolerant schemes that not only have low qubit overhead but also comply with geometrical interaction constraints are therefore necessary. In this work, we combine flag fault tolerance with quantum circuit mapping, to enable an efficient flag-bridge approach to implement FT QEC on near-term devices. We further show an example of performing the Steane code error correction on two current superconducting processors and numerically analyze their performance with circuit level noise. The simulation results show that the QEC circuits that measure more stabilizers in parallel have lower logical error rates. We also observe that the Steane code can outperform the distance-3 surface code using flag-bridge error correction. In addition, we foresee potential applications of the flag-bridge approach such as FT computation using lattice surgery and code deformation techniques.QCD/Almudever LabQuTechComputer Engineerin