Analyzing the divide between FPGA academic and commercial results

The pinnacle of success for academic work is often achieved by having impact on commercial products. In order to have a successful transfer bridge, academic evaluation flows need to provide representative results of similar quality to commercial flows. A majority of publications in FPGA research use the same set of known academic CAD tools and benchmarks to evaluate new architecture and tool ideas. However, it is not clear whether the claims in academic publications based on these tools and benchmarks translate to real benefits in commercial products. In this work we compare the latest Xilinx commercial tools and products with these well-known academic tools to identify the gap in the major figures of merit. Our results show that there is a significant 2.2X gap in speed-performance for similar process technology. We have also identified the area-efficiency and runtime divide between commercial and academic tools to be 5% and 2.2X, respectively. We show that it is possible to improve portions of the academic flow such as ABC logic optimization to match the quality of commercial tools at the expense of additional runtime. Our results also show that depth reduction, which is often used as the main figure of merit for logic optimization papers does not translate to post-routing timing improvements. We finally discuss the differences between academic and commercial benchmark designs. We explain the main differences and trends that may influence the topic choice and conclusions of academic research. This work emphasizes how difficult it is to identify the relevant FPGA academic work that can provide meaningful benefits for commercial products

Caffeine and Sodium Bicarbonate Supplementation Alone or Together Improve Karate Performance

Background: The ergogenic properties of acute caffeine (CAF) and sodium bicarbonate (NaHCO3) ingestion on athletic performance have been previously investigated. However, each sport has unique physiological and technical characteristics which warrants optimizing supplementations strategies for maximizing performance. This study examined the effects of CAF and NaHCO3 ingestion on physiological responses and rate of perceived exertion during a Karate-specific aerobic test (KSAT) in competitive karatekas. Methods: In a double-blind, crossover, randomized placebo-controlled trial, eight Karatekas underwent five experimental conditions including control (CON), placebo (PLA), CAF, NaHCO3, and CAF + NaHCO3 before completing KSAT. Capsules containing 6 mg/kg BW CAF were consumed 50 min prior to a KSAT whilst 0.3 g/kg BW NaHCO3 was consumed for 3 days leading to and 120, 90, and 60 min prior to a KSAT. Time to exhaustion (TTE), rate of perceived exertion (RPE), and blood lactate (BL) were measured before, immediately after and 3 min following KSAT. Results: TTE was significantly greater following CAF, NaHCO3, and CAF + NaHCO3 consumption compared to PLA and CON. However, the differences between CAF, NaHCO3, and CAF+NaHCO3 were not statistically significant (p \u3e 0.05). BL increased significantly from baseline to immediately after and 3 min following KSAT in all conditions (p \u3c 0.01), while RPE at the end of KSAT was not significantly different between conditions (p = 0.11). Conclusions: Karate practitioners may benefit from the ergogenic effects of CAF and NaHCO3 when consumed separately or together

Micropropagation of lisianthus (Eustoma grandiflorum), an ornamental plant

Abstract Lisianthus (Eustoma grandiflorum) is an ornamental plant with beautiful flowers. Micropropagation is a powerful tool for large-scale propagation of ornamental plants. The shoot tips explants from Lisianthus were cultured on MS medium supplemented with concentrations of 0, 0.5, 1 and 2 mg/L of NAA and KIN. Here, we present a simple and reliable strategy for micropropagation of Eustoma grandiflorum in presence of the single growth regulator, KIN, which enables the production of stock plants. Multiple shoots containing roots can be obtained simultaneously on MS basal medium only supplemented with 0.5-1 mg/L KIN. Shoot tips media supplemented with 1 mg/L KIN without NAA resulted in the best shoot length per explant (2.058 cm) and shoot number per explant (2.62). Also, the most number of nodes per explant (8.86) was obtained in medium containing 0.5 mg/L KIN without NAA. The highest root number per shoot (2.40) was seen in medium supplemented with 2 mg/L KIN + 0.5 mg/L NAA. Shoot tips grown in medium containing 2 mg/L NAA without KIN showed the most callus formation. The results of this study revealed that the best shoot proliferation was achieved in MS medium supplemented with 0.5 or 1 mg/L KIN without NAA. Regenerated plants were transferred to peat and perlite (1:1) after hardening and they showed 100% survival

Optimal Placement and Sizing of Distributed Generation Units Using Co-Evolutionary Particle Swarm Optimization Algorithms

Today, with the increase of distributed generation sources in power systems, it’s important to optimal location of these sources. Determine the number, location, size and type of distributed generation (DG) on Power Systems, causes the reducing losses and improving reliability of the system. In this paper is used Co-evolutionary particle swarm optimization algorithm (CPSO) to determine the optimal values of the listed parameters. Obtained results through simulations are done in MATLAB software is presented in the form of figure and table in this paper. These tables and figures, show how to changes the system losses and improving reliability by changing parameters such as location, size, number and type of DG. Finally, the results of this method are compared with the results of the Genetic algorithm (GA) method, to determine the performance of each of these methods. DOI: http://dx.doi.org/10.11591/telkomnika.v13i2.7026

Logic Devices (CPLDs). Commercially available FPGAs consist

In this paper we present new technology mapping algorithms for use in a programmable logic device (PLD) that contains both lookup tables (LUTs) and PLA-like blocks. The technology mapping algorithms partially collapse circuits to reduce either area or depth, and pack the circuits into a minimum number of LUTs and PLA-like blocks. Since no other technology mapping algorithm for this problem has been previously published, we cannot compare our approach to others. Instead, to illustrate the importance of this problem we use our algorithms to investigate the benefits provided by a PLD architecture with both LUTs and PLA-like blocks compared to a traditional LUT-based FPGA. The experimental results indicate that our mixed PLD architecture is more area-efficient than LUT-based FPGAs by up to 29%, or more depth-efficient by up to 75%. 1

Novel architectures and synthesis methods for high capacity field programmable devices

grantor: University of TorontoField Programmable Devices (FPDs) are rapidly gaining popularity for implementing digital circuits due to their attractive features such as reprogrammability and fast time to market. This thesis proposes two new architectures, called the Hybrid Field Programmable Architecture (HFPA) and the Computational Field Programmable Architecture (CFPA). The HFPA represents a combination of two existing technologies: Field Programmable Gate Arrays (FPGAs) based on LUTs, and Complex Programmable Logic Devices based on PLA-like blocks. The methodology used for development of this new architecture is based on analysis of a large set of benchmark circuits, in which we determine what types of logic resources best match the needs of the circuits. The HFPA is evaluated by technology mapping a set of circuits into the new architecture and estimating the total chip area needed and the depth for each circuit, compared to the area and depth that would be required if only LUTs were available. Using the technology mapping algorithms, we partially collapse circuits to reduce either area or depth, and pack the circuits into a minimum number of LUTs and PLA-like blocks. We present results for a number of mapping trade-offs to evaluate the benefits of the HFPA. Our experimental results indicate that LUT-based FPGAs need 11% more chip area and 65% higher depth than the HFPA. Another mapping trade-off, which minimizes the area of the circuits, shows that the area and depth benefits of the proposed architecture over traditional FPGAs are 25% and 21%, respectively. This thesis also considers a more aggressive step to improve the area-efficiency of FPDs by focusing on a special class of applications. In this dissertation, the CFPA is introduced that is targeted at compute-intensive applications. These applications are important because of their use in the expanding markets in data processing. We explain the logic resources in the CFPA and a synthesis method with which we have mapped a number of circuits to the new architecture. According to our results, the computational architecture is more area-efficient than general-purpose FPGAs by a factor of 2.8 times for the benchmark circuits that are considered.Ph.D

The Effect of Perceptual – Motor Experience on Motor Development Quotient of Fine and Gross Motor Skills in 5-8-Month-Old Infants

The purpose of this study was to investigate the effect of perceptual – motor experience on motor development quotient of fine and gross motor skills in infants. Fifteen 5-8-month-old healthy infants participated randomly in this study and were divided homogenously into two groups (experimental and control) according to their age. Experimental group had 36 training sessions, each session an hour at a perceptual – motor enriched environment. Peabody motor development scale was used to evaluate fine and gross motor skills. Data were analyzed by independent t test. Results indicated a significant difference in mean score of motor development quotient between fine motor skills (p=0.004) and gross motor skills (p=0.02). These findings showed that training and experience had a positive effect on motor development generally and on motor development quotient of fine and gross motor skills specifically. In other words, training and experience were positive factors of fundamental and basic motor skills development of the infants in both groups. These results are in line with the perspective of dynamic systems of motor development

Dynamic power consumption in VirtexII FPGA family," presented at the

ABSTRACT This paper analyzes the dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) by taking advantage of both simulation and measurement. Our target device is Xilinx Virtex™-II family, which contains the most recent and largest programmable fabric. We identify important resources in the FPGA architecture and obtain their utilization, using a large set of real designs. Then, using a number of representative case studies we calculate the switching activity corresponding to each resource. Finally, we combine effective capacitance of each resource with its utilization and switching activity to estimate its share of power consumption. According to our results, the power dissipation share of routing, logic and clocking resources are 60%, 16%, and 14%, respectively. Also, we concluded that dynamic power dissipation of a Virtex-II CLB is 5.9µW per MHz for typical designs, but it may vary significantly depending on the switching activity

Dynamic Power Consumption in Virtex™-II FPGA Family

This paper analyzes the dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) by taking advantage of both simulation and measurement. Our target device is Xilinx Virtex^TM-II family, which contains the most recent and largest programmable fabric. We identify important resources in the FPGA architecture and obtain their utilization, using a large set of real designs. Then, using a number of representative case studies we calculate the switching activity corresponding to each resource. Finally, we combine effective capacitance of each resource with its utilization and switching activity to estimate its share of power consumption. According to our results, the power dissipation share of routing, logic and clocking resources are 60%, 16%, and 14%, respectively. Also, we concluded that dynamic power dissipation of a Virtex-II CLB is 5.9W per MHz for typical designs, but it may vary significantly depending on the switching activity