31 research outputs found
New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata
Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies,
promising alternative to CMOS technology due to faster speed, smaller size,
lower power consumption, higher scale integration and higher switching
frequency. Also, power dissipation is the main limitation of all the nano
electronics design techniques including the QCA. Researchers have proposed the
various mechanisms to limit this problem. Among them, reversible computing is
considered as the reliable solution to lower the power dissipation. On the
other hand, adders are fundamental circuits for most digital systems. In this
paper, Innovation is divided to three sections. In the first section, a method
for converting irreversible functions to a reversible one is presented. This
method has advantages such as: converting of irreversible functions to
reversible one directly and as optimal. So, in this method, sub-optimal methods
of using of conventional reversible blocks such as Toffoli and Fredkin are not
used, having of minimum number of garbage outputs and so on. Then, Using the
method, two new symmetric and planar designs of reversible full-adders are
presented. In the second section, a new symmetric, planar and fault tolerant
five-input majority gate is proposed. Based on the designed gate, a reversible
full-adder are presented. Also, for this gate, a fault-tolerant analysis is
proposed. And in the third section, three new 8-bit reversible
full-adder/subtractors are designed based on full-adders/subtractors proposed
in the second section. The results are indicative of the outperformance of the
proposed designs in comparison to the best available ones in terms of area,
complexity, delay, reversible/irreversible layout, and also in logic level in
terms of garbage outputs, control inputs, number of majority and NOT gates
New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata
Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies,
promising alternative to CMOS technology due to faster speed, smaller size,
lower power consumption, higher scale integration and higher switching
frequency. Also, power dissipation is the main limitation of all the nano
electronics design techniques including the QCA. Researchers have proposed the
various mechanisms to limit this problem. Among them, reversible computing is
considered as the reliable solution to lower the power dissipation. On the
other hand, adders are fundamental circuits for most digital systems. In this
paper, Innovation is divided to three sections. In the first section, a method
for converting irreversible functions to a reversible one is presented. This
method has advantages such as: converting of irreversible functions to
reversible one directly and as optimal. So, in this method, sub-optimal methods
of using of conventional reversible blocks such as Toffoli and Fredkin are not
used, having of minimum number of garbage outputs and so on. Then, Using the
method, two new symmetric and planar designs of reversible full-adders are
presented. In the second section, a new symmetric, planar and fault tolerant
five-input majority gate is proposed. Based on the designed gate, a reversible
full-adder are presented. Also, for this gate, a fault-tolerant analysis is
proposed. And in the third section, three new 8-bit reversible
full-adder/subtractors are designed based on full-adders/subtractors proposed
in the second section. The results are indicative of the outperformance of the
proposed designs in comparison to the best available ones in terms of area,
complexity, delay, reversible/irreversible layout, and also in logic level in
terms of garbage outputs, control inputs, number of majority and NOT gates
4H-SiC MESFET with darin-side and undoped region for modifying charge distribution and high power applications
In this paper, a novel MESFET with an undoped region (DS-UR) and drain side-double recessed 4H-SiC metal semiconductor field effect transistor (MESFET) is presented. The key idea in this work is to modify the charge concentration and electric field distribution to improving breakdown voltage (VBR) and the maximum output power density (Pmax). The charge distribution plays an important role in determining device characteristics. Two-dimensional and two-carrier device simulation demonstrate that the VBR and Pmax are improved about 57% and 50% compared to source side-double recessed 4H-SiC MESFET (SS) structure, respectively which are important for high power applications
Time Management Approach on a Discrete Event Manufacturing System Modeled by Petri Net
Discrete event system,  Supervisory control,  Petri Net, Constraint  This paper presents a method to manage the time in a manufacturing system for obtaining an optimized model. The system in this paper is modeled by the timed Petri net and the optimization is performed based on the structural properties of Petri nets. In a system there are some states which are called forbidden states and the system must be avoided from entering them. In Petri nets, this avoidance can be performed by using control places. But in a timed Petri net, using control places may lead to decreasing the speed of systems. This problem will be shown on a manufacturing system. So, a method will be proposed for increasing the speed of the system without using control places
500 V breakdown voltage in βâGa2O3 laterally diffused metalâoxideâsemiconductor fieldâeffect transistor with 108 MW/cm2 power figure of merit
Abstract The authorsâ present a siliconâonâinsulator (SOI) laterally diffused metalâoxideâsemiconductor fieldâeffect transistor (LDMOSFET) with βâGa2O3 , which is a large bandgap semiconductor (βâLDMOSFET), for increasing breakdown voltage (VBR) and power figure of merit. The fundamental purpose is to use a βâGa2O3 semiconductor instead of silicon material due to its large breakdown field. The characteristics of βâLDMOSFET are analysed to those of standard LDMOSFET, such as VBR, ONâresistance (RON), power figure of merit (PFOM), and radio frequency (RF) performances. The effects of RF, such as gateâdrain capacitance (CGD), gateâsource capacitance (CGS), transit frequency (fT), and maximum frequency of oscillation (fMAX) have been investigated. The βâLDMOSFET structure outperforms performance in the VBR by increasing it to 500 versus 84.4 V in standard LDMOSFET design. The suggested βâLDMOSFET has RON ~ 2.3 mâŚ.cmâ2 and increased the PFOM (VBR2/RON) to 108.6 MW/cm2. All the simulations are done with TCAD and simulation models are calibrated with the experimental data
Simplification of a Petri Net controller in industrial systems
This paper deals with the problem of forbidden states in discrete event systems modeled by Petri Net. To avoid the forbidden states, some constraints which are called Generalized Mutual Exclusion Constraints can be assigned to them. Enforcing these constraints on the system can be performed using control places. However, when the number of these constraints is large, a large number of control places must be connected to the system which complicates the model of controller. In this paper, the objective is to propose a general method for reducing the number of the mentioned constraints and consequently the number of control places. This method is based on mixing some constraints for obtaining a constraint verifying all of them which is performed using the optimization algorithms. The obtained controller after reducing the number of the control places is maximally permissive