A Graphene-based Hot Electron Transistor

We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call Graphene Base Transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 50.000.Comment: 18 pages, 6 figure

Numerical Simulation of Advanced CMOS and Beyond CMOS Nanoscale Transistors

There is a growing consensus in the electron device community that the 32nm node could be the last technology node based on the conventional silicon planar MOSFET, due to the physical limitations of this technology. Several new approaches are under investigation in order to reach the requirement of the International Technology Roadmap for Semiconductors beyond the 32nm technology node; some studies are focused on new device architectures that allow a better control of the gate over the channel, while other ones propose to substitute silicon in the channel with high-mobility materials. The physics-based modeling of these new devices is extremely important because it is supposed to guide the electron device industry in the choice of the best device structures for the future technology nodes. In this context, the aim of this PhD thesis is to investigate two of these innovative technology options: the FinFET and the nanowires device architectures and the graphene based transistors. To this purpose, we developed several TCAD simulation tools based on advanced modeling techniques. In the first part of the thesis we developed a solver for the simulation of the electrostatics in the channel section of nanowires and FinFETs with realistic shape, based on an innovative numerical approach, the Pseudospectral method. Thanks to the remarkable accuracy of this approach (i.e. an exponential decrease of the approximating error with the number of discretization points), we were able to develop a very efficient simulator, which vastly outperforms solvers based on standard numerical approaches such as the finite differences. Moreover, we compared our approach with another innovative method, the Discrete Geometric Approach, in the simulation of the electrostatics of realistic devices. The second part of the PhD was focused on the simulation of graphene, the innovative material with very interesting physical properties discovered in 2004. First we developed a novel and general approach for the exact solution of the linearized Boltzmann transport equation; we applied the proposed method to the calculation of the graphene bilayer low-field mobility: the obtained results are quite consistent with the experimental values found in the literature. We also demonstrate that the most common approach used in the literature for the estimation of the low-field mobility (i.e. the Momentum Relaxation Time approach) introduces non negligible errors in the considered case. We thus developed also a semi-classical transport simulator based on the Monte Carlo approach for the modeling of the uniform transport in bilayer graphene. Our simulations showed that the saturation velocity in this material is much higher than in silicon; moreover, with respect to monolayer graphene, the saturation velocity is higher in bilayer graphene only at high carrier densities. Finally, we developed a semi-classical model for RF graphene FETs based on the Monte Carlo approach including a novel local model for band-to-band tunneling. The simulator, that was validated by comparison with full quantum results, improves the range of applications of semi-classical Monte Carlo models for graphene based transistors. Using this simulator we found that the band-to-band tunneling is responsible for the poor saturation of the current in GFETs transistors; moreover, we studied the effect of the scattering and of the gate length on the performance of this device and we found that the scattering has a non negligible influence on the main RF figures of merit even in short channel devices

Phonon Limited Uniform Transport in Bilayer Graphene Transistors

We report modeling results for low-field mobility and velocity saturation in bilayer graphene based on a newly developed semiclassical transport Monte-Carlo simulator validated by comparison with momentum relaxation time (MRT) calculations. We show that remote phonons originating in the dielectric stack are expected to strongly affect the mobility, although assessing their actual influence at high inversion charge requires the development of an accurate model for dynamic screening. When the applied bias opens the energy gap, the mobility is significantly reduced. The saturation velocity is expected to be as high as 3 7107 cm/s and less degraded than mobility by bandgap opening

Simulation of the Performance of Graphene FETs With a Semiclassical Model, Including Band-to-Band Tunneling

We assess the analog/RF intrinsic performance of graphene FETs (GFETs) through a semiclassical transport model, including local and remote phonon scattering as well as band-to-band tunneling generation and recombination, validated by comparison with full quantum results over a wide range of bias voltages. We found that scaling is expected to improve the fT , and that scattering plays a role in reducing both the fT and the transconductance also in sub-100-nm GFETs. Moreover, we observed a strong degradation of the device performance due to the series resistances and source/drain to channel underlaps

High Performance Tuning Tips For Communications Adapters: Token Ring, Ethernet And Atm

In this paper, we will present performance tuning tips (including step-by-step instructions for modifying the appropriate parameters) for Ethernet, Token Ring and ATM adapters installed under some of the most common operating systems (Windows 95 and NT, NetWare, OS/2, and AIX). IBM communications adapters will be used as examples throughout. We will discuss the theory behind adapter performance tuning as we go. We will then discuss some workstation and networking hardware features, capacities, etc. that will affect final observed adapter performance. Finally, we will recommend some industry standard benchmarks that may be used to measure the performance resulting from the tuning process. ITIRC KEY WORDS Performance Tuning Ethernet Adapter Token Ring Adapter LAN Adapter ATM Adapter TCP/IP Tuning IPX Tuning iii iv CONTENTS ABSTRACT . . . . . . . . . . . . . . . . . . . . . iii ITIRC KEYWORDS . . . . . . . . . . . . . . . . . . iii INTRODUCTION . . . . . . . . . . . . . . . . . . . ..

Piezoresistive Properties of Suspended Graphene Membranes under Uniaxial and Biaxial Strain in Nanoelectromechanical Pressure Sensors

Monolayer graphene exhibits exceptional electronic and mechanical properties, making it a very promising material for nanoelectromechanical devices. Here, we conclusively demonstrate the piezoresistive effect in graphene in a nanoelectromechanical membrane configuration that provides direct electrical readout of pressure to strain transduction. This makes it highly relevant for an important class of nanoelectromechanical system (NEMS) transducers. This demonstration is consistent with our simulations and previously reported gauge factors and simulation values. The membrane in our experiment acts as a strain gauge independent of crystallographic orientation and allows for aggressive size scalability. When compared with conventional pressure sensors, the sensors have orders of magnitude higher sensitivity per unit area

Investigation of strain engineering in FinFETs comprising experimental analysis and numerical simulations

his study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced mobility enhancement in FinFETs and guidelines for device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel holographic technique. A large vertical compressive strain is observed in metal gate FinFETs, and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFET lateral interfaces with respect to (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of stress components in the fin width, height, and length directions on the mobility of both n- and p-type FinFETs and to identify optimal stress configurations. Finally, self-consistent Monte Carlo simulations are used to investigate how the most favorable stress configurations can improve the on current of nanoscale MOSFETs