Area efficient test circuit for library standard cell qualification

High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction

Cost-efficient standard cell library timing and power validation techniques

A standard cell library contains functional blocks with known electrical characteristics,which are characterized to obtain the following parameters: propagation delay, output transition time, power representation, and capacitance. Standard cell libraries are widely applied by industry designers to the implementation of application-specific integrated circuit (ASIC) designs. Such application is facilitated by the provision of extremely high gate density and excellent electrical performance. Early validation of the characterization data for the standard cells on physical silicon is required to guarantee the correct implementation of the final design in silicon functions. The silicon validation processes correlate the characterized values with the actual silicon performance. However, this process is costly in terms of design and fabrication. Moreover, testing the process on wafer silicon measurement validation is difficult in terms of test time and because of equipment limitation. In this research, an enhanced silicon validation method was developed to validate the libraries using the basics of the delay chain technique. The method was tested by applying two new approaches to designing test element group (TEG) circuits. These two approaches are sharing load between multi-chains and input control for multi-input gates. These proposed methods can reduce the cost of fabrication through total silicon area reduction of the test chip achieved by decreasing the total number of transistors required in the design. The total number of I/O PADs required in the validation process can also be reduced, and the test time can be enhanced. The effectiveness of our proposed approaches was evaluated on several test chips that consist of an inverter, a multi-input NAND, and NOR gates as basic cells of combinational logic circuits in the library. Test chips were designed to verify the functionality of the design and to validate timing delays and dynamic and leakage power, which are influenced by cell output loading and cell input transition parameters. The test chip was tested at operating environments that match simulation corners to cover datasheet-specified operating conditions