Design of RF Oscillators for Wireless Digital Transmitters

Cost reduction is one of the main driving forces for integration. As such, advanced CMOS technologies offer excellent digital functionality and high-density integration capabilities. Properties that persuade designers to exploit new digitally assisted approaches rather than following conventional analogue techniques. Using these new concepts, fully integrated transmitters that operate from baseband up to the pre-power amplifier (PA) stage entirely in the digital domain have become feasible. However, this imposes many coupling issues for different parts of the transceiver, such as the local oscillator. One of the primary building blocks of the transmitter is an oscillator and each modern digital transmitter has to have at least one oscillator, which normally has tough specifications imposed by the standard and transceiver architecture. This thesis focuses on the design of digitally controlled oscillators which could have excellent phase noise, very fine frequency resolution, small footprint and wide tuning range. Moreover, a simple yet an efficient architectural solution for the problem of local oscillator pulling, which will likely be the main cause degrading spectral purity of the TX output in multi radio SoCs has been proposed.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc

Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division

In modern RF system on chips (SoCs), the digital content consumes up to 85% of the IC chip area. The recent push to integrate multiple RF-SoC cores is met with heavy resistance by the remaining RF/analog circuitry, which creates numerous strong aggressors and weak victims leading to RF performance degradation. A key such mechanism is injection pulling through parasitic coupling between various LC-tank oscillators as well as between them and strong transmitter (TX) outputs. Any static or dynamic frequency proximity between aggressors (i.e., oscillators and TX outputs) and victims (i.e., oscillators) that share the same die causes injection pulling, which produces unwanted spurs and/or modulation distortion. In this paper, we propose and demonstrate a new frequency planning technique of a multicore TX where each LC-tank oscillator is separated from other aggressors beyond its pulling range. This is done by breaking the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels using digital fractional divider based on a phase rotation. Each oscillator’s center frequency can be fractionally separated by ~28% but, at the same time, both producing closely spaced frequencies at the phase rotator outputs. The injection-pulling spurs are so far away that they are insignificantly small (?80 dBc) and coincide with the second harmonic of the carrier. This method is experimentally verified in a two-channel system in 65-nm digital CMOS, each channel comprising a high-swing class-C oscillator, frequency divider, and phase rotator.MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc

A Tiny Quadrature Oscillator Using Low-Q Series LC Tanks

A new quadrature oscillator topology is proposed, which arranges four low-Q series LC tanks in a ring structure driven by inverters operating in class-D. With a very small area of 0.007 mm^2 that is comparable to conventional ring oscillators, this oscillator has 7–20 dB better phase noise FoM of 177 dB. It is widely tunable for nearly an octave from 2.66 to 4.97 GHz.MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc

Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise

In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology. We then apply it to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules. The oscillator is realized in digital 65-nm CMOS as a dualcore LC-tank oscillator based on a high-swing class-C topology. It is tunable within 4.07-4.91 GHz, while drawing 39-59 mA from a 2.15 V power supply. The measured PN is -146.7 dBc/Hz and -163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from a 4.07 GHz carrier, which makes it the lowest reported normalized PN of an integrated CMOS oscillator. Straightforward expressions for PN and interconnect resistance between the cores are derived and verified against circuit simulations and measurements. Analysis and simulations show that the interconnect resistance is not critical even with a 1% mismatch between the cores. This approach can be extended to a higher number of cores and achieve an arbitrary reduction in PN at the cost of the power and area.Electronic