Acceleration of hardware code coverage closure using machine learning

Abstract. With the ever-increasing system-on-chip (SoC) design complexity, the verification of such systems is becoming more and more challenging and extremely time consuming. Hence, the human efforts put in this task seem neither to be sufficient, nor efficient enough anymore to maintain a good pace with the escalating market demands. In this work, we will present a descent way of utilizing machine learning (ML) for reducing the overhead of hardware design verification in terms of resources consumption. Our focus in this thesis is especially about the time spent on coverage closure that usually occupies a great deal of the whole verification time. Both deep learning (DL) and reinforcement learning (RL) are deployed for this purpose, in two different experiments, in order to come out with the most coherent way to accomplish the coverage closure task. On one hand, neural networks (NNs) were used to help visualize whether a stimulus is worth to run the simulation with, by predicting the coverage number that it would generate. On the other hand, Q-learning was used to predict the minimal set of tests needed to reach some code coverage goal, by optimizing and reducing the set of tests while still achieving the same coverage levels. The results of these experiments show captivating findings. First, the root mean square error (RMSE) of the neural network models was about 3 and 5 in predicting two different coverage values, respectively, which is quite good for a training run on a small dataset. Second, our Q-agent was able to do better than the coverage ranking utility of the simulation tool by almost 43%, where it reduced the number of tests from 63, as suggested by the simulator, to 36. This should remarkably reduce the required number of simulations in weekly regressions, hence result in a huge gain in time and resources. Both of these approaches aim at reducing the engineers’ efforts through accelerating the verification process and automating it, which frees some of the engineers’ time and allow them to focus on more important matters