Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

The implementation and operation of the nonvolatile ferroelectric memory (NVM) tunnel field effect transistors with silicon-doped HfO2 is proposed and theoretically examined for the first time, showing that ferroelectric nonvolatile tunnel field effect transistor (Fe-TFET) can operate as ultra-low power nonvolatile memory even in aggressively scaled dimensions. A Fe-TFET analytical model is derived by combining the pseudo 2-D Poisson equation and Maxwell’s equation. The model describes the Fe-TFET behavior when a time-dependent voltage is applied to the device with hysteretic output characteristic due to the ferroelectric’s dipole switching. The theoretical results provide unique insights into how device geometry and ferroelectric properties affect the Fe-TFET transfer characteristic. The recently explored ferroelectric, silicon-doped HfO2 is employed as the gate ferroelectric. With the ability to engineer ferroelectricity in HfO2 thin films, a high-K dielectric well established in memory devices, the silicon-doped HfO2 opens a new route for improved manufacturability and scalability of future 1-T ferroelectric memories. In the current research, a Si:HfO2 based Fe-TFET with large memory window and low power dissipation is designed and simulated. Utilizing our presented model, the device characteristics of a Fe-TFET that takes full benefits from Si:HfO2 is compared with the same devices using well-known perovskite ferroelectrics. Finally, the Fe-TFET is compared with a conventional ferroelectric memory transistor highlighting the advantages of using tunneling memory devices

The Electron\u2013Hole Bilayer TFET: Dimensionality Effects and Optimization

An extensive parameter analysis is performed on the electron-hole bilayer tunnel field-effect transistor (EHBTFET) using a 1-D effective mass Schr\uf6dinger-Poisson solver with corrections for band non-parabolicity considering thin InAs, In0.53Ga0.47As, Ge, Si0.5Ge0.5, and Si films. It is found that depending on the channel material and channel thickness, the EHBTFET can operate either as a 2-D-2-D or 3-D-3-D tunneling device. InAs offers the highest I ON, whereas for the Si and Si0.5Ge0.5 EHBTFETs, significant current levels cannot be achieved within a reasonable voltage range. The general trends are explained through an analytical model that shows close agreement with the numerical results

Condition for the negative capacitance effect in metal–ferroelectric–insulator–semiconductor devices

In this paper, we report a detailed study of the negative capacitance field effect transistor (NCFET). We present the condition for the stabilization of the negative capacitance to achieve the voltage amplification across the active layer. The theory is based on Landauʼs theory of ferroelectrics combined with the surface potential model in all regimes of operation. We demonstrate the validity of the presented theory on experimental NCFETs using a gate stack made of P(VDF-TrFE) and SiO2. The proposed analytical modeling shows good agreement with experimental data

Electrical characterization of high performance, liquid gated vertically stacked SiNW-based 3D FET for biosensing applications

A 3D vertically stacked silicon nanowire (SiNW) field effect transistor featuring a high density array of fully depleted channels gated by a backgate and one or two symmetrical platinum side-gates through a liquid has been electrically characterized for their implementation into a robust biosensing system. The structures have also been characterized electrically under vacuum when completely surrounded by a thick oxide layer. When fully suspended, the SiNWs may be surrounded by a conformal high-κ gate dielectric (HfO2) or silicon dioxide. The high density array of nanowires (up to 7 or 8 × 20 SiNWs in the vertical and horizontal direction, respectively) provides for high drive currents (1.3 mA/μm, normalized to an average NW diameter of 30 nm at VSG = 3 V, and Vd = 50 mV, for a standard structure with 7 × 10 NWs stacked) and high chances of biomolecule interaction and detection. The use of silicon on insulator substrates with a low doped device layer significantly reduces leakage currents for excellent Ion/Ioff ratios >106 of particular importance for low power applications. When the nanowires are submerged in a liquid, they feature a gate all around architecture with improved electrostatics that provides steep subthreshold slopes (SS 10 μS) while allowing for the entire surface area of the nanowire to be available for biomolecule sensing. The fabricated devices have small SiNW diameters (down to dNW ∼ 15–30 nm) in order to be fully depleted and provide also high surface to volume ratios for high sensitivities