Physical simulation of GaN based HEMT

Recent improvements in the understanding and fabrication of GaN have led to its application in high frequency communication and high voltage switching systems. Requirement for operation at even higher frequency and voltages is driving the research currently on design of GaN based devices which can operate at frequencies above 30 GHz and voltages up to 100 V. Reliability issues with GaN based devices operating in such conditions and lack of understanding of various phenomena are some of the factors hindering their widespread commercial development. There is a need to understand the device operation by developing a simulation model, as close to reality as possible, which could be, further, used to optimize the device design for high frequency and power operation. Recent improvements in the understanding and fabrication of GaN have led to its application in high frequency communication and high voltage switching systems. Requirement for operation at even higher frequency and voltages is driving the research currently on design of GaN based devices which can operate at frequencies above 30 GHz and voltages up to 100 V. Reliability issues with GaN based devices operating in such conditions and lack of understanding of various phenomena are some of the factors hindering their widespread commercial development. There is a need to understand the device operation by developing a simulation model, as close to reality as possible, which could be, further, used to optimize the device design for high frequency and power operation. This thesis work reports the design and development of a physical simulation model of AlGaN/GaN High Electron Mobility Transistor (HEMT) using commercial software (Synopsys, Sentaurus TCAD). The model is calibrated against measurement data. The results show a close matching with measured data, although some discrepancies have been found in the linear region of DC operation and high frequency regime of AC analysis. It is observed that trap density and their energy level (surface and bulk) play an important role in device characteristics. Effects of including quantum calculations in the model are analyzed. Various methods to improve the operating frequency have been investigated. The results show that by tuning the drain to gate distance, gate length and AlGaN thickness, AC characteristics can be improved significantly (fmax > 150 GHz). The influence of changing the epitaxial layer structure (adding more layers) on the device's AC characteristics is analysed to find an optimum design for high frequency applications

On the Apparent Non-Arrhenius Temperature Dependence of Charge Trapping in Iota Iota Iota V/High-k MOS Stack

© 1963-2012 IEEE. Operating temperature has a significant imp-act on the reliability of metal-oxide-semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ( Δ Neff) at operating condition typically shows an Arrhenius temperature dependence with EA 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77-373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture-emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total ΔV th measured in biaserature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance.status: publishe

On the temperature dependence of frequency dispersion in C-V measurements of III-V MOS devices and its application in spatial profiling of border traps

This paper presents a detailed investigation of the temperature dependence of frequency dispersion observed in capacitance-voltage (C-V) measurements of III-V metal-oxide-semiconductor (MOS) devices. The dispersion in the accumulation region of the capacitance data is found to change from 4%–9% (per decade frequency) to ∼0% when the temperature is reduced from 300 K to 4 K in a wide range of MOS capacitors with different gate dielectrics and III-V substrates. We show that such significant temperature dependence of C-V frequency dispersion cannot be due to the temperature dependence of channel electrostatics, i.e., carrier density and surface potential. We also show that the temperature dependence of frequency dispersion, and hence, the capture/emission process of border traps can be modeled by a combination of tunneling and a “temperature-activated” process described by a non-radiative multi-phonon model, instead of a widely believed single-step elastic tunneling process

Monolithic Integration of Nano-Ridge Engineered InGaP/GaAs HBTs on 300 mm Si Substrate

Nano-ridge engineering (NRE) is a novel method to monolithically integrate III–V devices on a 300 mm Si platform. In this work, NRE is applied to InGaP/GaAs heterojunction bipolar transistors (HBTs), enabling hybrid III-V/CMOS technology for RF applications. The NRE HBT stacks were grown by metal-organic vapor-phase epitaxy on 300 mm Si (001) wafers with a double trench-patterned oxide template, in an industrial deposition chamber. Aspect ratio trapping in the narrow bottom part of a trench results in a threading dislocation density below 106∙cm−2 in the device layers in the wide upper part of that trench. NRE is used to create larger area NRs with a flat (001) surface, suitable for HBT device fabrication. Transmission electron microscopy inspection of the HBT stacks revealed restricted twin formation after the InGaP emitter layer contacts the oxide sidewall. Several structures, with varying InGaP growth conditions, were made, to further study this phenomenon. HBT devices—consisting of several nano-ridges in parallel—were processed for DC and RF characterization. A maximum DC gain of 112 was obtained and a cut-off frequency ft of ~17 GHz was achieved. These results show the potential of NRE III–V devices for hybrid III–V/CMOS technology for emerging RF applications

Effective Contact Resistivity Reduction for Mo/Pd/n-In0.53Ga0.47 as Contact

status: publishe