Interconnect Aging—Physics to Software

Device reliability or lifetime is often non-negotiable and crucial for sensitive applications such as medical devices, autonomous vehicles and space crafts. Inevitable technology advancement (e.g. miniaturization) has added unwelcome complications and unpredictability to the aging problem. Reliability of VLSI chips is jeopardized by mass transport in metallic interconnects. Material migration is caused by electrical, mechanical and thermal phenomena, and, therefore, is a complicated process. While all aspects of material migration have been studied, a comprehensive investigation that can explain and include all those phenomena simultaneously remains unsolved. Inaccuracies in modeling and predicting aging processes in wires cause that chipmakers often overdesign interconnects. This is an undesirable and expensive approach in terms of time and cost. In modern technologies, the predicted lifetime, aging, and failure mechanisms in interconnect very often do not match the observed behaviors. Unrealistic models used in CAD tools are the main culprit of such incompatibilities. In general, two situations may occur: (1) in some cases, the models may wrongly scrutinize reliability in unfailing parts and consequently impose unnecessary design tightening and (2) in some other cases, the models may underestimate serious reliability problems causing unpredicted behaviors or catastrophic failures to occur. The existing models for reliability evaluation are usually pessimistic in case of interconnect voiding and optimistic when extrusions occur. Time-consuming and not converging reliability assessments, as well as undesired chip behaviors, are the common expensive outcome of such models.We revisit the underlying physics of aging processes in dual-damascene copper lines. We demonstrate, that the simplistic modeling is the cause of the incompatibility of the existing models. We study all three main aging processes: electromigration, thermo-migration, and stress migration and offer several comprehensive yet compact models for realistic assessment of interconnect aging. These models explain many observations that have been inexplicable for decades. Ultimately, a computer-aided design tool, RAIN, is developed based on the proposed models and is capable of assessing the reliability of industry standard complex multi-layer, multi-segment interconnect networks. This tool can be readily integrated into other verification signoffs phases such as performance, timing, and power analyses. RAIN takes as inputs: (1) interconnect design, (2) technology specifications, (3) initial stress and temperature, (4) IR drop and lifetime requirements. It analyzes and assesses reliability and delivery requirements of all nets, and provides a report on voltage limitations, thermal violations and expected lifetime. It is validated on a wide spectrum of experimental results performed on various industry benchmarks

Reliability analysis of logic networks

Bibliography: p. 68-76The reliability of digital devices is threatened by various sources, ranging from architectural issues and process variations to environmental fluctuations and noises. Also, error generated by these sources are inherently stochastic and transient. This makes reliability analysis an indispensable step of circuit design. Several reliability evaluation methods have been proposed for binary logic circuit. However, correlation of reliability with the input and gate errors and reliability analysis of multivalued circuits have not been investigated as of yet. This research investigates the reliability of switching circuits based on probabilistic models, and examines their applicability to multivalued circuits. We also develop an algebraic method for evaluating reliability of multivalued circuits. We further discuss how reliability of k-ary logic networks depends on radix k, input and gate errors. Thereafter, we propose a probabilistic model for representing and detecting faults. This research also studies behavior of probabilistic logic networks for very large (continuous) radix