Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates

The first contribution of our paper is that we propose a platform, a design strategy, and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. Using a SASEBO-GII field-programmable gate array (FPGA) board as a common platform, combined with well defined hardware and software interfaces, we compare all 256-bit version candidates with respect to area, throughput, latency, power, and energy consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specification for the SHA-3 module on our testing platform. The second contribution is that we provide both FPGA and 90-nm CMOS application-specific integrated circuit (ASIC) synthesis results and thereby are able to compare the results. Our third contribution is that we release the source code of all the candidates and by using a common, fixed, publicly available platform, our claimed results become reproducible and open for a public verification. © 1993-2012 IEEE.status: publishe

円管開口端からの圧力波の放出による衝撃音のパッシブコントロール

When a high-speed train enters a tunnel, a compression wave is generated ahead of the train and propagates to the tunnel exit. This pressure wave emits from the exit of the tunnel as an impulsive wave which makes a blast sound. The object of this paper is to show a passive way to reduce the level of the blast sound. The effects of annular boxes at the exit of a circular tube were investigated experimentally and numerically. As a result, relations between the size of the passive silencer and noise reduction rate have been clarified which suggests a suitable design factor for an exit annular box