NUV-HD SiPMs with metal-filled trenches

In this paper we present the performance of a new SiPM that is sensitive to blue light and features narrow metal-filled trenches placed in the area around the single-photon avalanche diodes (SPADs) that allow an almost complete suppression the internal optical crosstalk. In particular, we show the benefits of this technological upgrade in terms of electro-optical SiPM performance when compared to the previous technology which had only a partial optical screening between the SPADs. The most relevant effect is the much higher bias voltage that can be applied to the new device before the noise diverges. This allows to optimize and improve both the photon detection efficiency and the single-photon time resolution. We also coupled the SiPMs to LYSO scintillators to verify the performance for possible application in Positron-Emission Tomography. Thanks to the better electro-optical features we were able to measure an improved coincidence time resolution. Furthermore, the optimal voltage operation region is substantially larger, making this SiPM more suitable for real system application where thousands of channels have to provide stable and reproducible performance

Exploration of Gate Trench Module for Vertical GaN devices

The aim of this work is to present the optimization of the gate trench module for use in vertical GaN devices in terms of cleaning process of the etched surface of the gate trench, thickness of gate dielectric and magnesium concentration of the p-GaN layer. The analysis was carried out by comparing the main DC parameters of devices that differ in surface cleaning process of the gate trench, gate dielectric thickness, and body layer doping. . On the basis of experimental results, we report that: (i) a good cleaning process of the etched GaN surface of the gate trench is a key factor to enhance the device performance, (ii) a gate dielectric >35-nm SiO2 results in a narrow distribution for DC characteristics, (iii) lowering the p-doping in the body layer improves the ON-resistance (RON). Gate capacitance measurements are performed to further confirm the results. Hypotheses on dielectric trapping/detrapping mechanisms under positive and negative gate bias are reported.Comment: 5 pages, 10 figures, submitted to Microelectronics Reliability (Special Issue: 31st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2020

NUV-HD SiPMs with Metal-filled Trenches

In this contribution we would like to present a breakthrough improvement of the optical crosstalk between SPADs in SiPMs. In the framework of a collaboration between FBK and Broadcom we developed narrow metal-filled trenches that greatly suppress the optical crosstalk while maintaining a high fill factor and, in turn, photon detection efficiency. In particular, the new metal in trench detector (NUV-HD-MT) features an internal crosstalk almost 10 times lower than previous NUV-HD FBK SiPMs and can operate up to 17 V of excess bias voltages without any divergence of the correlated noise. The higher operating bias compensates the small loss in fill factor due to the insertion of the metal layer in the trenches and allows the NUV-HD-MT to reach PDE in excess of 60% with 40 μm cells. Together with a SiPM layout optimized for timing, the extended bias range allows to operate the detector with higher gain and low level of correlated noise, improving the CTR performance below 90 ps using 4x4 mm2 detectors coupled to 3x3x5 mm3 LYSO:Ce crystals and readout by a conventional front-end. The characteristics described above allow this detector to be considered as a good candidate for the upgrade of ToF-PET machines

3D integration technologies for custom SiPM: From BSI to TSV interconnections

Progress in 3D interconnecting technologies paved the way for a new generation of Silicon Photomultipliers (SiPM) and Single Photon Avalanche Diode (SPAD): hybrid devices which combine the integrated functionalities of the digital SiPM with the high performance of custom technologies, like low noise and high detection efficiency. Recently, Fondazione Bruno Kessler (FBK) has been working on the implementation of recently developed 3D integration technologies, on SiPMs devices, to improve both performances and functionalities by creating backside-illuminated (BSI) devices and Through Silicon Vias (TSV) interconnections. Two different technology platforms have been investigated: a BSI design for near-infrared (NIR) sensitive SiPMs and TSV interconnections for near- and vacuum-ultraviolet (NUV/VUV) sensitive detectors. For NIR applications, electrical characterization of ultra-thin (about ) SiPM wafers with a metal reflector on the frontside has shown an improved photon detection efficiency (PDE) when operated in BSI configuration compared with non-thinned front-side illuminated (FSI) devices, allowing at the same time full high-segmentation access to the SiPM output from the front-side. Instead, for NUV/VUV applications, a FSI stacked approach is considered more suitable since the junction depth needs to be shallower. In this case, TSV interconnections using two different approaches (named Via-Mid and Via-Last) have been implemented allowing the placement of the contacts on the backside of the wafer

Silicon Photomultipliers technologies for 3D integration

Progress in 3D interconnecting technologies paved the way to a new generation of Silicon Photomultipliers (SiPM) by combining the integrated functionalities of the digital SiPM with the high performance, in terms of noise and efficiency, of the analog SiPM. Recently, FBK has been developing new 3D integration technologies, specifically designed for SiPMs, to improve performances and functionalities by using backside-illuminated (BSI) devices and Through Silicon Vias (TSV) interconnections. Two different technology platforms have been identified: a BSI design for NIR and TSV interconnections for NUV/VUV SiPMs. Two R&D batches are under development to demonstrate the feasibility as well as robustness and reliability of both the technologies. For NIR applications, electrical characterization of ultra-thin SiPM wafers with a metal reflector on the front side has shown an improved photon detection efficiency when operated in BSI configuration compared with thinned front-side illuminated (FSI) devices, allowing at the same time high-segmentation access to the SiPM output from the front-side. Instead, for NUV/VUV applications, a FSI stacked approach is more suitable since the junction depth needs to be shallower to absorb short wavelengths. In this case, TSV interconnections have been implemented allowing to place the contacts on the backside of the wafer

Degradation Mechanisms of GaN HEMTs with p-Type Gate under Forward Gate Bias Overstress

This paper investigates the degradation of GaN-based HEMTs with p-type gate submitted to positive gate bias stress. Based on combined electrical and optical testing, we demonstrate the existence of different degradation processes, depending on the applied stress voltage VGstress: 1) for VGstress< 7 V, no significant degradation is observed, thus demonstrating a good stability of the analyzed technology; 2) for 7 V< VGstress < 11.5 V, a negative shift in threshold voltage (Vth) is observed, well correlated with a decrease in the gate leakage current and of the luminescence signal associated with hole injection. The negative Vth shift is ascribed to the trapping of holes in the AlGaN and/or p-GaN/AlGaN interface; and 3) for VGstress 12 V, threshold voltage recovers its initial value. This is ascribed to a net-negative charge, generated either by the trapping of electrons injected from the 2-D electron gas to the AlGaN or to the de-trapping of the holes injected in 2). The results described within this paper provide relevant information for understanding the degradation dynamics of normally off GaN transistors submitted to extremely high gate voltage levels far beyond maximum use