Extensive reliability analysis of Tungsten dot NC devices embedded in HfAlO high-k dielectric under NAND (FN/FN) operation

In this work we present an extensive reliability and performance evaluation of Tungsten dot Nanocrystal (NC) devices under NAND mode of operation. Improvement in performance and reliability was observed with scaling W and L. The use of better high-k processing is proposed to improve the reliability. We also propose a numerical simulation model for NC memory devices using transient capacitive charging model. The approach is very generic and computationally less extensive than the previous works

The integration of high-k dielectric on two-dimensional crystals by atomic layer deposition

We investigate the integration of Al2O3 high-k dielectric on two-dimensional (2D) crystals of boron nitride (BN) and molybdenum disulfide (MoS2) by atomic layer deposition (ALD). We demonstrate the feasibility of direct ALD growth with trimethylaluminum and water as precursors on both 2D crystals. Through theoretical and experimental studies, we found that the initial ALD cycles play the critical role, during which physical adsorption dominates precursor adsorption at the crystal surface. We model the initial ALD growth stages at the 2D surface by analyzing Lennard-Jones potentials, which could guide future optimization of the ALD process on 2D crystals. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3703595

Germanium oxynitride gate interlayer dielectric formed on Ge(100) using decoupled plasma nitridation

Germanium Oxynitride (GeON) gate interlayer (IL) dielectric formed using decoupled plasma nitridation (DPN) technique is compared with GeO2 and thermally nitrided GeON ILs for Ge gate stack applications using n-channel capacitors and transistors. Lower nitrogen concentration and roughness at the GeON/Ge interface lead to lower midgap interface trap density (D-it) and 1.5 x higher electron mobility for the DPN versus thermally nitrided GeON IL. DPN GeON IL also exhibits enhanced thermal stability till 575 degrees C at the expense of a small degradation in D-it versus GeO2 IL, making it a more viable gate IL dielectric on Ge channels. (C) 2013 AIP Publishing LLC

High Performance 400 degrees C p(+)/n Ge Junctions Using Cryogenic Boron Implantation

We report high performance Ge p(+)/n junctions using a single, cryogenic (-100 degrees C) boron ion implantation process. High activation >4 x 10(20) cm(-3) results in specific contact resistivity of 1.7 x 10(-8) Omega-cm(2) on p(+)-Ge, which is close to ITRS 15 nm specification (1 x 10(-8) Omega-cm(2)) and nearly 4.5x lower than the state of the art (8 x 10(-8) Omega-cm(2)). Cryogenic implantation is shown to enable solid-phase epitaxial regrowth and lower junction depth through amorphization of the surface Ge layer. These improvements in Ge p(+)/n junctions can pave the way for future high mobility Ge p-MOSFETs

Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts

Metal-induced-gap-states model for Fermi-level pinning in metal-semiconductor contacts has been extended to metal-interfacial layer (IL)-semiconductor (MIS) contacts using a physics-based approach. Contact resistivity simulations evaluating various ILs on n-Ge indicate the possibility of forming low resistance contacts using TiO2, ZnO, and Sn-doped In2O3 (ITO) layers. Doping of the IL is proposed as an additional knob for lowering MIS contact resistance. This is demonstrated through simulations and experimentally verified with circular-transfer length method and diode measurements on Ti/n(+)-ZnO/n-Ge and Ti/ITO/n-Ge MIS contacts. (C) 2013 AIP Publishing LLC

Enhanced Ge n(+)/p Junction Performance Using Cryogenic Phosphorus Implantation

In this paper, we present a detailed study of temperature-based ion implantation of phosphorus dopants in Ge for varying dose and anneal conditions through fabricated n(+)/p junctions and n-type MOSFETs (nMOSFETs). In comparison with room temperature (RT) (25 degrees C) and hot (400 degrees C) implantation, cryogenic (-100 degrees C) implantation with a dose of 2.2e15 cm(-2) followed by a (400 degrees C) rapid thermal annealing leads to 1) lower junction leakage with higher activation energy and 2) lower sheet resistance with higher dopant activation and shallower junction depth. Gate-last Ge nMOSFETs fabricated using cryogenic implanted n(+)/p source/drain junction (2.2e15 cm(-2)) exhibit lower OFF-current (upto 5x) and higher ON-current compared with RT (25 degrees C) and hot (400 degrees C) implanted nMOSFETs. This paper demonstrates that cryogenic implantation (-100 degrees C) can enable high-performance Ge nMOSFETs by alleviating the problems of lower activation and high diffusion of phosphorus in Ge

Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology

FinFET technology is prone to suffer from line edge roughness (LER)-based V-T variation with scaling. It also lacks a simple implementation of multiple V-T technology needed for power management. To address these challenges, in this paper we present an epitaxially defined FinFET (EDFinFET) as an alternate to FinFET architecture for nodes 15 nm and beyond. We show by statistical simulations that EDFinFET reduces overall V-T variability with an 80% reduction in LER-based variability in comparison with FinFETs. We present dynamic threshold MOS (DTMOS) configuration of EDFinFET using the available body terminal to individual transistors. The DTMOS configuration reduces LER-based variability by 90% and overall variability by 59%. It also has excellent subthreshold slope (SS) and gives 43% higher I-ON compared with FinFETs. Meanwhile, EDFinFET shows poorer SS and lower I-ON than FinFET due to single gate control. However, it is capable of multiple V-T, which leads to circuit level power optimization

Development of a 3D simulator for metal Nanocrystal (NC) flash memories under NAND operation

A 3D simulator for metal Nanocrystal (NC) flash is developed and verified with published experimental data. The simulator is capable of extracting physical parameters and predicting their impact on cell performance. The simulator is used to optimize cell design and analyze performance with scaling, NC randomness and NC number fluctuations