Wide Range High Precision CMOS Exponential Circuit Based on Linear Least Squares Approach

A new strategy to implement exponential circuit in CMOS technology is presented in this paper. The proposed method is based on the new approximation function optimized by linear least squares approach to extend the output dynamic range. The current mode method is employed for realization of circuits, because of simple circuitry and intuitive topology. Unlike to the some reported circuits which were designed in the subthreshold region, the proposed design operates in the saturation region which provides acceptable bandwidth for the circuit. In order to validate the circuit performance, the post layout simulation results are presented using HSPICE and Cadence with TSMC level 49 (BSIM3v3) parameters for 0.18 μm CMOS technology. The results demonstrate 78 dB output dynamic range with the linearity error less than ±0.5 dB which shows a remarkable improvement in comparison with previously reported works. A bandwidth of 67 MHz, maximum power consumption of 0.326 mW under supply voltage of 1.5 V, and 0.77% error for temperature variations are further achievement of the design

High-Precision CMOS Analog Computational Circuits Based on a New Linearly Tunable OTA

Implementation of CMOS current-mode analog computational circuits are presented in this paper. A new Linearly Tunable OTA is employed in a modified structure as a basic building block for implementation of the circuits either linear or nonlinear functions. The proposed trans-conductance amplifier provides a constant Gm over a wide range of input voltage which allows the implementation of high precision computational circuits including square rooting, squaring, multiplication and division functions. Layout pattern of the proposed circuit confirms that the circuit can be implemented in 102μm*69μm active area. In order to verify the performance of the circuits, the post layout simulation results are presented through the use of HSPICE and Cadence with TSMC level 49 (BSIM3v3) parameters for 0.18 μm CMOS technology, where under supply voltage of 1.8 V, the maximum relative error of the circuits within 500 µA of input range is about 11 μA (2.2 % error) and the THD remains as low as 1.2 % for the worst case. Moreover, the power dissipation of the complete structure is found to be 0.66 mW