Enabling robust automotive electronic components in advanced CMOS nodes

28th European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Bordeaux, FRANCE, SEP 25-28, 2017International audienceIn this work, we have demonstrated that many elements are needed on top of conventional foundry reliability knowledge to enable robust automotive products in compliance with all restrictive norms. For intrinsic reliability, bothreliability models (a design compatible WLR description), and dynamic aging compensation schemes are required. For extrinsic failures, screening procedures require well documented usage and are shown in use for volume production to bring the failure rate level down below 1 ppm automotive target. Altogether, the global approach developed in STMicroelectronics enable robust automotive products based on controlled and validated procedures. (C) 2017 Published by Elsevier Ltd

Resilient Automotive Products through Process, Temperature and Aging Compensation Schemes

International audienc

Performance vs. reliability adaptive body bias scheme in 28 nm 8214 nm UTBB FDSOI nodes

27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Halle, GERMANY, SEP 19-22, 2016International audienceThis paper shows the advantages of using body bias. Experiments are performed in 14 nm and 28 nm UTBB FDSOI transistors and ring oscillators (ROs). The impact of body bias on performance and reliability is highlighted. The body biasing offers significant advantages for adapting the tradeoff between reliability and performance in logic circuits without changing the design margins. With FDSOI technology, we have an additional degree of freedom of process variability compensation by using body bias voltage (Adaptive Body Bias, ABB) next to supply voltage compensation used before. We show that ABB compensation technique presents better results for a complete power optimization. (C) 2016 Elsevier Ltd. All rights reserved

A coupled study by floating-gate and charge-pumping techniques of hot carrier-induced defects in submicrometer LDD n-MOSFET's

International audienceThe creation of defects by hot-carrier effect in submicrometer (0.85µm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptor-like oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from Vd/8 to Vd/) by hot-hole and/or hot-electron injections, and their generation rates (1E-9 and 1E-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the Id-Vg degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the Id-Vg degradation

Resilient Automotive Products through Process, Temperature and Aging Compensation Schemes

International audienc

Comment on "Hot-Hole induced negative oxide charges in N-MOSFET's"

International audienceFor the original article see ibid., vol. 42, p. 1473 (1995). The commenters state that a clear proof of the generation of electron traps under hot-hole injections and a clear distinction from the effect of stress-induced interface states have been given by them in a paper (see ibid., vol. 40, p. 773, 1993) previous to the work reported by Weber et al. Also, the consequences of the creation of these defects in AC lifetime predictions have been extensively discussed by Mistry and Doyle (see ibid., vol. 40, p.96, 1993 and IEEE Electron Device Lett., vol. 12, p. 492, 1991). Detrapping experiments extensively used by Weber et al. are another independent evidence of such a creation of electron traps by hot-hole injections in n-MOSFET's, and the suggestion of new data acquisition to take into account the effects of such electron traps in the determination of lifetimes is a key point to further development, especially as far as operating conditions of analog CMOS circuits are considered. In reply the authors remark that the paper by Vuillaume et al. was inadvertently left off the reference list as they were unaware of its existence and as the paper is certainly relevant to the issue being discussed, it should have been included in the reference list. Also the authors give several arguments why they believe that their technique using time-dependent changes in the multiplication factor M is superior to either charge pumping or floating gate measurements for differentiating between the two types of negative charge created by hot-hole injection: interface traps and oxide traps

Managing electrical reliability in consumer systems for improved energy efficiency

International audienc

Stress induced leakage currents in N-MOSFETs submitted to channel hot carrier injections

International audienceIn this study, we report on the electrical properties of the stress induced leakage current which appears through a 4.7 nm-thick SiO2 gate oxide of N-channel metal-oxide-semiconductor field effect transistors after localized channel hot carrier injections and Fowler–Nordheim uniform injections. We show that channel hot hole injections are able to induce a stress leakage current leading at longer times to a gate current versus gate voltage similar to the one obtained after uniform injections in the Fowler–Nordheim mode, and well fitted by a Schottky law. However, the kinetics of both degradation modes differ. Other localized hot carrier injection modes (channel hot electron injections) appear to be less efficient in producing stress induced leakage current. Hole injection at the Si/SiO2 interface, present in both channel hole injections and negative gate voltage Fowler–Nordheim stresses via the anode hole injection mechanism, is found to be the key phenomenon leading to stress induced leakage current generation

Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI

International audienceAging induced degradation mechanisms occurring in digital circuits are of a greater importance in the latest technologies. Monotonic degradation such as Bias Temperature Instability (BTI) or Hot Carrier Injection (HCI) but also sudden degradation such as Dielectric Breakdown (DB) are identified as the major sources of reliability hazard. The impact of these phenomena on the digital circuits is usually observed in terms of timing degradations and thus may result in setup/hold violation. In this paper we will focus on the impact of aging related degradation mechanisms on timing. In-situ monitor is a promising strategy to measure timing slacks and to provide pre-error warnings prior to timing violation. In this paper, we have developed a dedicated test structure to measure and benchmark the behavior of different monitors. The design of monitors is mostly based on delay elements. Three types of delays are proposed in this paper: flip-flop's Master delay, Buffers delay and Passive delay. In addition, we investigate the impact of global and local variations on the accuracy of the measurements by providing complete monitors characterization. The technology used for the test structure and in-situ monitors is 28nm Fully Depleted Silicon On Insulator. Experimental results show a good agreement with SPICE simulation. Finally the proposed in-situ monitors will be compared and their applications to circuit aging prediction will be discussed