Timing error tolerance in nanometer ICs

Abstract—Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency

A built-in-test circuit for RF differential low noise amplifiers

This paper presents an efficient, low-cost, built-in test (BIT) circuit for radio frequency differential low noise amplifiers (DLNAs). The BIT circuit detects amplitude alterations at the outputs of the DLNA, due to parametric or catastrophic faults, and provides a single digital Pass/Fail indication signal. A triple modular redundancy approach has been adopted for the BIT circuit design to avoid possible yield loss in case of a malfunctioning test circuitry. The technique has been evaluated on a typical CMOS RF DLNA and simulation results are presented. © 2006 IEEE

A design for testability scheme for CMOS LC-tank voltage controlled oscillators

In this paper, a new Design for Testability (DFT) scheme is proposed, for the testing of LC-tank CMOS Voltage Controlled Oscillators (VCOs). The proposed test-circuit is capable of detecting hard (catastrophic) and soft (parametric) faults, injected in the VCO. The test result is provided by a digital Fail/Pass signal. Simulation results reveal the effectiveness of the proposed circuit. The overall silicon area requirement of the proposed DFT scheme is negligible

Analog-to-digital interface for heterodyne receivers

The analysis of the Intermediate Frequency (IF) section of a heterodyne receiver employing IF sampling, based on its Carrier-to-Interference ratio (C/I), yields various options on filtering, amplification, conversion to digital and interfacing to base-band. These options are considered using Bit Error Rate (BER) simulations, leading to an optimized design for the IF section and the interface to base-band of the heterodyne receiver

A 0.35 mu m SiGeBICMOS front end for GSM low if cellular receiver applications

This work presents the design and simulation of a cellular receiver front end for GSM applications implemented in 0.35 SiGe BiCMOS technology. The Low Noise Amplifier is designed using Bipolar transistors, and achieves a voltage gain of 17 dB at 950 MHz, while its Noise Figure is suppressed to 1.9 dB in the same frequency region. The resulting 1 dB compression point is -12 dBm and the IIP3 -3 dBm. The mixer is a double balanced Gilbert cell performing an IIP3 of 14 dBm, while the single sideband noise figure is around 12 dB. The whole structure is oriented to low IF receiver applications while the overall power consumption is 31 mW provided from a 3.3 V power supply

Adjustable RF mixers alternate test efficiency optimization by the reduction of test observables

A method for the optimization of the efficiency of alternate tests for adjustable RF mixers is presented in this paper. Alternate tests provide a cost- and time-effective substitute for their conventional specification-based counterparts by attempting to predict rather than directly measuring a circuit's performance from its response to suitable test stimuli. In order to provide post-manufacture yield recovery through calibration, integrated RF circuits - especially nanometric circuits - are often designed to present some form of adjustability. Such a property offers a set of discrete states of operation, from which a performance-compliant state is selected by calibration. In general, an alternate test can be conducted for each discrete state of operation, thus providing a large set of test observables from which regression models can be constructed to predict performance in all available states. However, test time and cost concerns impose that the derivation of the predictive models should be performed through an optimization procedure that aims to select a subset of the test observables that minimizes a certain cost criterion. In this paper, alternate tests for adjustable RF mixers are considered where the test response consists of dc voltage levels that appear at certain circuit nodes while the mixer operates in homodyne mode. Selection algorithms are applied to determine the optimum observables from the test response. Simulations on a typical RF mixer, designed in an 0.18μ CMOS technology, have shown significant improvement in the corresponding alternate test efficiency. © 1982-2012 IEEE

A test and calibration strategy for adjustable RF circuits

A test and calibration strategy suitable for adjustable RF circuits is presented in this paper. Certain performance-affecting circuit elements are designed to be digitally controllable, providing the capability to adjust the performance characteristics of a circuit's instance around their post-fabrication values, throughout a set of discrete states of operation. The alternate test methodology is adopted for test and calibration and a set of optimally selected test observables is used to develop regression models for the prediction of the circuit's performance characteristics in every state of operation. In the test phase, measurements of the test observables are obtained from a subset of the circuit's states. The processing of these observables provides accurate prediction of the RF circuit's performance characteristics in all available states and enables the discrimination of defect-free from defective circuits. The latter is further accomplished by the exploitation of an extended superset of the test observables, the use of which intends to maximize fault coverage. Moreover, the predicted performance characteristics are also used to examine compliance with the specifications and to allow calibration of the RF circuit by identifying the appropriate state of operation at which all specifications are met and, consequently, by forcing the circuit to operate in this specific state. The efficiency of the proposed technique has been validated by its application to a typical differential RF Mixer designed in a 0.18 μm CMOS technology. Simulation results have been obtained and assessed. © 2012 Springer Science+Business Media New York

A design for testability technique for mixed-signal differential circuits

In this paper a new DFT scheme is proposed suitable for testing Mixed signal differential circuits. The proposed testing-scheme is capable of detecting single catastrophic faults injected into the circuit under test. These faults can be either shorts and opens or bridgings between non contiguous nodes of the circuit. The test result is provided by a digital Fail/Pass indication signal. Exhaustive simulations have revealed the effectiveness of the proposed technique in terms of fault coverage and cost

State reduction for efficient digital calibration of analog/RF integrated circuits

Calibration of analog/radio-frequency (RF) integrated circuits addresses the problem of yield loss that is a result of the increased variability commonly observed in nanoscale processes. In order to compensate for increased yield loss, calibration techniques have been developed that are applied to fabricated chips, aiming at the restoration of a circuit’s performance to its acceptable range of values that are defined by the specifications. To allow calibration, adjustable elements are introduced that provide multiple states of a circuit’s operation through built-in tuning knobs. Digital calibration—that refers to the case of discrete tuning knob settings—is performed by switching to a circuit’s state at which all performance characteristics are restored to their specified ranges. Due to the large number of performance characteristics of interest a large space of tuning knob settings should be explored, that leads to a series of practical considerations that need to be addressed, such as increased times required for calibration preparation and conduction, or chip area overhead if built-in tuning knobs are used. In this paper we present a method to maintain a desired level of yield recovery through the exploitation of only a minimum number of calibration states, also ensuring low cost by shortening calibration times and reducing chip area overhead. The proposed method is assessed through case studies conducted on a typical RF mixer designed in a 180 nm CMOS technology. © 2016, Springer Science+Business Media New York

A built-in self-test scheme for differential ring oscillators

In this paper a new Built-In Self-Test (BIST) scheme is proposed suitable for testing differential voltage controlled ring oscillators. The proposed testing-scheme is capable of detecting single realistic faults of the circuit under test. These faults can be either short or bridging faults between circuit nodes or open faults at the circuit branches. The test result is provided by a digital Fail/Pass indication signal. Exhaustive simulations have revealed the effectiveness of the proposed technique regarding its fault coverage