A Flexible LDPC/Turbo Decoder Architecture

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm2. The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE Turbo codes. Running at 500 MHz clock frequency, the decoder can sustain up to 600 Mbps LDPC decoding or 450 Mbps Turbo decoding.NokiaNokia Siemens Networks (NSN)XilinxTexas InstrumentsNational Science Foundatio

Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links,” GlobeCom

Abstract — Implementing a multi-tone (MT) architecture for high-speed backplane electrical links is difficult given the tight power and complexity constraints in this application. This paper proposes an approach that incorporates a baseband (BB) channel and a few passband (PB) channels. In this MT system interchannel interference (ICI) and inter-symbol interference (ISI) are eliminated through fractionally spaced equalization at the transmitter and feedback equalization at the receiver. The design is modeled as a MIMO system, and optimal equalizer coefficients to minimize the transmit peak voltage are found by casting the optimization as a Second Order Conic (SOC) problem. In addition, for systems that need adaptation, we show how equalizer and power allocation coefficients can be obtained (sub optimally) using Zero Forcing (ZF) optimization. The effect of transmitter and receiver clock jitter are modeled in a way that can be included in both SOC and ZF optimizations, and the performance of this system is compared to more conventional baseband examples. It is shown that this AMT system can be built with complexity/power similar to a comparable performance baseband system, but has the ability to scale to higher bit rates. I

A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems

In this paper, a new technique for characterization of digital-toanalog converters (DAC) used in wideband applications is described. Unlike the standard narrowband approach, this technique employs Least Square Estimation to characterize the DAC from dc to any target frequency. Characterization is performed using a random sequence with certain temporal and probabilistic characteristics suitable for intended operating conditions. The technique provides a linear estimation of the system and decomposes nonlinearity into higher-order harmonics and deterministic periodic noise. The technique can also be used to derive the impulse response of the converter, predict its operating bandwidth, and provide far more insight into its sources of distortion. 1

A 24Gb/s Software Programmable Multi-Channel Transmitter

A 24Gb/s transmitter with a digital linear equalizer is implemented in 90nm CMOS technology. It supports 4channel Analog Multi-Tone (AMT) transmission, where each channel supports 3GSym/Sec 4PAM data, as well as a variety of baseband (BB) modes ranging from 2 PAM to 256 PAM. The transmitter operates at maximum rate of 24Gb/s, dissipating 510mW of power in 0.8mm 2

Design and VLSI implementation for a WCDMA multipath searcher

The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading due to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 mu m CMOS technology and requires only 150 k gates for a total area of 1.5 mm(2) consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator