Design and cryogenic operation of a hybrid quantum-CMOS circuit

Silicon-On-Insulator nanowire transistors of very small dimensions exhibit quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for larger dimensions, allowing to design integrated circuits. Using the same process, we have co-integrated a FET-based ring oscillator circuit operating at cryogenic temperature which generates a radio-frequency (RF) signal on the gate of a nanoscale device showing Coulomb oscillations. We observe rectification of the RF signal, in good agreement with modeling

Cryogenic operation of SOI electron pumps and ring oscillators

International audienc

Shadow-scan design with low latency overhead and in-situ slack-time monitoring

Conference of 19th IEEE European Test Symposium, ETS 2014 ; Conference Date: 26 May 2014 Through 30 May 2014; Conference Code:106457International audienceShadow-scan solutions are proposed in order to facilitate the implementation of faster scan flip-flops (FFs) with optional support for in-situ slack-time monitoring. These solutions can be applied to system FFs placed at the end of timing-critical paths while standard-scan cells are deployed in the rest of the system. Automated scan stitching and automated test pattern generation (ATPG) can be performed transparently with commercial tools. The generated test patterns cover not only the mission logic but also the monitoring infrastructure. The latency of itc'99 benchmark circuits could be reduced with up to 10% while the stuck-at fault coverage (FC) was preserved as compared to circuit versions with full standard-scan design. Limited variations in the number of test patterns were observed when support for in-situ slack-time monitoring was provided

A Light Unsaturated Hydrocarbon and Hydrogen Peroxide as Future Green Propellants for Bipropellant Thrusters

In the framework of the PulCheR project, an experimental test campaign on a 40 N bipropellant thruster prototype has been carried out with the aim of assessing the attainable propulsive performance in steady state conditions of 98% concentration hydrogen peroxide and propyne. The experimental specific impulse measured at sea level with the matched conical nozzle of the prototype has been 213 s that corresponds to an extrapolated vacuum specific impulse for a high expansion area ratio bell-contoured nozzle higher than 320 s. The light unsaturated hydrocarbon has been effectively ignited by the oxygen-rich hot gases produced by the catalytic decomposition of the hydrogen peroxide

Fully Integrated Spiking Neural Network with Analog Neurons and RRAM Synapses

International audienceThis paper presents, to the best of the authors' knowledge, the first complete integration of a Spiking Neural Network, combining analog neurons and Resistive RAM (RRAM)-based synapses. The implemented topology is a perceptron, aimed at performing MNIST classification. An existing framework was tailored for offline learning and weight quantization. The test chip, fabricated in 130nm CMOS, shows well-controlled integration of synaptic currents and no RRAM read disturb issue during inference tasks (at least 750M spikes). The classification accuracy is 84%, with a 3.6 pJ energy dissipation per spike at the synapse and neuron level (up to 5x lower vs. similar chips using formal coding)

Advanced technologies for brain-inspired computing

Conference of 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 ; Conference Date: 20 January 2014 Through 23 January 2014; Conference Code:103285International audienceThis paper aims at presenting how new technologies can overcome classical implementation issues of Neural Networks. Resistive memories such as Phase Change Memories and Conductive-Bridge RAM can be used for obtaining low-area synapses thanks to programmable resistance also called Memristors. Similarly, the high capacitance of Through Silicon Vias can be used to greatly improve analog neurons and reduce their area. The very same devices can also be used for improving connectivity of Neural Networks as demonstrated by an application. Finally, some perspectives are given on the usage of 3D monolithic integration for better exploiting the third dimension and thus obtaining systems closer to the brain