Electronic Properties of Cu/n-InP Metal-Semiconductor Structures with Cytosine Biopolymer

This work shows that cytosine biomolecules can control the electrical characteristics of conventional Cu/n-InP metal-semiconductor contacts. A new Cu/n-InP Schottky junction with cytosine interlayer has been formed by using a drop cast process. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of Cu/cytosine/n-InP structure were investigated at room temperature. A potential barrier height as high as 0.68 eV has been achieved for Cu/cytosine/n-InP Schottky diodes, which have good I-V characteristics. This good performance is attributed to the effect of interfacial biofilm between Cu and n-InP. By using C-V measurement of the Cu/cytosine/n-InP Schottky diode the diffusion potential and the barrier height have been calculated as a function of frequency. Also, the interface-state density of the Cu/cytosine/n-InP diode was found to vary from $2.24 \times 10^{13} eV^{-1} cm^{-2}$ to $5.56 \times 10^{12} eV^{-1} cm^{-2}$

Current-voltage-temperature analysis of inhomogeneous Au/n-GaAs Schottky contacts

The forward current-voltage (I-V) characteristics of Au/n-GaAs Schottky barrier diodes (SBDs) have been studied over a wide temperature range (80–300 K). The barrier height inhomogeneities by assuming a Gaussian distribution of barrier heights at the interface were observed. The evaluation of the experimental I-V data reveals a non-linear increase of the zero-bias barrier height ($q\Phi _{0}$). To remove the spatial inhomogeneity of the barrier height based on small regions or patches and to increase the barrier height compared to the reference sample Au/n-GaAs, the front surface of the n-type GaAs semiconductor has been oxidized by the anodic oxidation method and metal/insulating/semiconductor (MIS) Au/n-GaAs SBDs have been formed. The ln($I_{0}/T^{2}$) versus 1/T and $q\Phi _{0}$ versus T plots of the MIS have exhibited the linear behavior in the temperature range of 80–300 K. Thus, the I-V data of the MIS diodes have obeyed the interfacial layer model due to the interfacial layer and it has been concluded that the inhomogeneity of the barrier height can be disappeared by a formed interfacial layer at the metal and semiconductor interface

Temperature-dependent Schottky barrier inhomogeneity of Ni/n-GaAs diodes

We have reported a study of the I–V characteristics of Ni/n-GaAs Schottky barrier diodes (SBDs) in a wide temperature range of 60–320 K by a step of 20 K, which are prepared by magnetron DC sputtering. The experimental I–V data of the device quite well obey the thermionic emission model at 300 and 320 K, respectively. The ideality factor and barrier height values have changed by change of the sample temperature, the case has been attributed to the presence of the lateral inhomogeneities of the barrier height. The barrier inhomogeneity has been explained by the Gaussian distribution models of barrier heights suggested by some authors, Y.-L. Jiang et al. [Chin. Phys. Lett. 19, 553 (2002)]; Y.-L. Jiang et al. [J. Appl. Phys. 93, 866 (2003)], and S. Chand, J. Kumar [Appl. Phys. A 65, 497 (1997)]. It has been seen that the SBH inhomogeneity of our Ni/n-GaAs SBD can be well described by Gaussian distribution model suggested by Y.-L. Jiang et al. [Chin. Phys. Lett. 19, 553 (2002)]; Y.-L. Jiang et al. [J. Appl. Phys. 93, 866 (2003)] over whole measurement temperature range. Moreover, the modified ln($I_{0}/T ^{2}$) versus $1/k(T+T_0^\ast)$ plot is obtained using a method developed for T0 anomaly in the literature. Richardson constant value of 3.37 A cm-2 K-2 for n-type GaAs was obtained from the modified Richardson plot

The effects of the time-dependent and exposure time to air on Au/epilayer n-Si Schottky diodes

A study on Au/n-Si Schottky barrier diodes (SBDs) parameters with and without thin native oxide layer fabricated on n-type Si grown by LPE (Liquid-Phase Epitaxy) technique has been made. The native oxide layer with different thicknesses on chemically cleaned Si surface was obtained by exposing the Si surfaces to clean room air before metal evaporation. The native oxide thicknesses of samples D2, D3, D4 and D5 are in the form D2 < D3 < D4 ≤ D5 depending on the exposing time. It has been seen that the value of the barrier height Φb of samples D2 (0.64 eV), D3 (0.66 eV), D4 (0.69 eV) and D5 (0.69 eV) increases with increasing the exposure time and tends to that of the initial sample D1 (the initial sample, 0.74 eV), and thus also their I − V curves. Especially, the experimental results related to the exposure time of the surfaces to clean air are close in agreement with recently results reported for the HF-treated n-Si surface during initial oxidation in air. Furthermore, it has been determined experimentally that ageing of the Au contacts on the oxidized epilayer Si leads to barrier height values close to those measured for Au on chemically cleaned surfaces

Temperature-dependent I-V characteristics in thermally annealed Co/p-InP contacts

We prepared the sputtered Co/p-InP Schottky diodes which consisted of as-deposited, and diodes annealed from 200 °C to 700 °C. The annealed samples were cooled from the annealing temperature down to room temperature, and then, their current-voltage (I-V) characteristics were measured. Schottky barrier height (SBH) at 300 K slightly decreases from 0.80 eV (for as-deposited sample) down to 0.77 eV (for the sample annealed at 400 °C) with the annealing temperature and then again increases up to 0.91 eV for the sample annealed at 700 °C. The I-V measurements were made in the sample temperature range of 60–400 K. It is seen that the SBH for each diode monotonically increases with increasing the sample temperature up to 400 K. In the sample temperature range of 60–400 K, the Co/p-InP SBD annealed at 400 °C has a lower ideality factor value than those of the as-deposited and 200 °C annealed SBDs at each sample temperature. Thus, remarkable apparent improvement of the diode parameters has been achieved by means of the thermal annealing. The improvement in the Co/p-InP interface due to the thermal annealing process has continued without deteriorating at each measurement temperature from 60 K to 400 K. Therefore, it has been concluded that the thermal annealing process translates the MS Schottky contacts into thermally more stable Schottky contacts

The Effect of Exposure Time to Clean Room Air on Characteristic Parameters of Au/Epilayer n - Si Schottky Diodes

A study has been made on determination and comparison of current-voltage (I-V) and capacitance-voltage (C-V) characteristics parameters of Au/n - Si Schottky barrier diodes (SBDs) with and without thin native oxide layer fabricated on n-type Si grown by LPE (Liquid-phase Epitaxy) technique. The native oxide layer with different thicknesses on chemically cleaned on Si surface were obtained by exposing the surfaces to clean room air before evaporating metal. The native oxide thicknesses of samples D2, D3, D4 and D5 are in the form D2 &lt; D3 &lt; D4 ? D5, depending on the exposing time. It has been seen that the values of barrier height ?b of samples D2(0.64 eV), D3(0.66 eV), D4(0.69 eV) and D5(0.69 eV) with the interfacial layer increased with increasing the exposure time and tended to that of the initial sample D1 (nonoxidezed sample, 0.74 eV), and thus also their I-V and C-V curves. The reverse current of sample D1 showed slight nonsaturating behavior. This "soft" behavior has been ascribed to the spatial inhomogeneity in the barrier heights at the MS interface. In particular, reverse bias curves of samples D2, D3, D4 and D5 have shown excellent saturation which may be attributed to the passivation of the semiconductor surface states by the native oxide layer which reduces the penetration of the wave functions of electron in the metal into the semiconductor. Especially, the I-V characteristics and experimental parameters of our devices are in agreement with recently reported results revealed by the pulsed surface photovoltage technique for the electronic properties of the HF-treated Si surface during initial oxidation in air

The effect of exposure time to clean room air on characteristic parameters of Au/Epilayer n-Si Schottky diodes

A study has been made on determination and comparison of current-voltage (I-V) and capacitance-voltage (C-V) characteristics parameters of Au/n-Si Schottky barrier diodes (SBDs) with and without thin native oxide layer fabricated on n-type Si grown by LPE (Liquid-phase Epitaxy) technique. The native oxide layer with different thicknesses on chemically cleaned on Si surface were obtained by exposing the surfaces to clean room air before evaporating metal. The native oxide thicknesses of samples D2, D3, D4 and D5 are in the form D2 < D3 < D4 \leq D5, depending on the exposing time. It has been seen that the values of barrier height Fb of samples D2(0.64 eV), D3(0.66 eV), D4(0.69 eV) and D5(0.69 eV) with the interfacial layer increased with increasing the exposure time and tended to that of the initial sample D1 (nonoxidezed sample, 0.74 eV), and thus also their I-V and C-V curves. The reverse current of sample D1 showed slight nonsaturating behavior. This ''soft'' behavior has been ascribed to the spatial inhomogeneity in the barrier heights at the MS interface. In particular, reverse bias curves of samples D2, D3, D4 and D5 have shown excellent saturation which may be attributed to the passivation of the semiconductor surface states by the native oxide layer which reduces the penetration of the wave functions of electron in the metal into the semiconductor. Especially, the I-V characteristics and experimental parameters of our devices are in agreement with recently reported results revealed by the pulsed surface photovoltage technique for the electronic properties of the HF-treated Si surface during initial oxidation in air

Electrical properties of safranine T/p-Si organic/inorganic semiconductor devices

We investigated the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of identically prepared safranine T/p-Si organic/inorganic Schottky devices (total 26 diodes) formed by evaporation of organic compound solution on p-Si semiconductor substrate. It was seen that the safranine T organic thin film on the p-Si substrate showed a good rectifying behavior. The barrier heights and ideality factors of all devices were extracted from the electrical characteristics. The mean barrier height and mean ideality factor from I-V measurements were calculated as 0.59±0.02 eV and 1.80±0.20, respectively. Also, the mean barrier height and mean acceptor doping concentration from C-V measurements were calculated as 0.67±0.10 eV and (6.96±0.37)×1014 cm-3, respectively. The discrepancy in the barrier height values obtained from I-V and C-V characteristics has been attributed to different nature of the measurements. The discrepancy between these values can also be due to the existence of the interfacial native oxide and the organic safranine T thin layer between the semiconductor substrate and top contact metal