The Reliability Value of Storage in a Volatile Environment

Author's final manuscript: September 29, 2011This paper examines the value of storage in securing reliability of a system with uncertain supply and demand, and supply friction. The storage is frictionless as a supply source, but it cannot be filled up instantaneously. The focus is on application to an energy network in which the nominal supply and demand are assumed to match perfectly, while deviations from the nominal values are modeled as random shocks with stochastic arrivals. Due to friction, the random shocks cannot be tracked by the main supply sources. Storage, when available, can be used to compensate, fully or partially, for the surge in demand or sudden drop in supply. The problem of optimal utilization of storage with the objective of maximizing system reliability is formulated as minimization of the expected discounted cost of blackouts over an infinite horizon. It is shown that when the stage cost is linear in the size of the blackout, the optimal policy is myopic in the sense that all shocks will be compensated by storage up to the available level of storage. However, when the stage cost is strictly convex, it may be optimal to curtail some of the demand and allow a small blackout in the interest of maintaining a higher level of reserve, which may help avoid a large blackout in the future. The value of storage capacity in improving reliability, as well as the effects of the associated optimal policies under different stage costs on the probability distribution of blackouts are examined.National Science Foundation (U.S.)Siemens-MIT Allianc

Distributed Stochastic Power Control in Ad-hoc Networks: A Nonconvex Case

Utility-based power allocation in wireless ad-hoc networks is inherently nonconvex because of the global coupling induced by the co-channel interference. To tackle this challenge, we first show that the globally optimal point lies on the boundary of the feasible region, which is utilized as a basis to transform the utility maximization problem into an equivalent max-min problem with more structure. By using extended duality theory, penalty multipliers are introduced for penalizing the constraint violations, and the minimum weighted utility maximization problem is then decomposed into subproblems for individual users to devise a distributed stochastic power control algorithm, where each user stochastically adjusts its target utility to improve the total utility by simulated annealing. The proposed distributed power control algorithm can guarantee global optimality at the cost of slow convergence due to simulated annealing involved in the global optimization. The geometric cooling scheme and suitable penalty parameters are used to improve the convergence rate. Next, by integrating the stochastic power control approach with the back-pressure algorithm, we develop a joint scheduling and power allocation policy to stabilize the queueing systems. Finally, we generalize the above distributed power control algorithms to multicast communications, and show their global optimality for multicast traffic.Comment: Contains 12 pages, 10 figures, and 2 tables; work submitted to IEEE Transactions on Mobile Computin

The value of storage in securing reliability and mitigating risk in energy systems

The paper examines the value of ramp-constrained storage in securing reliability and mitigating risk in energy systems with uncertain supply and demand, and friction in the main supply source. Reliability is defined as the expected discounted cost of energy deficits over an infinite horizon, whereas risk is defined as the probability of incurring a large energy deficit. The nominal supply and demand are assumed to match perfectly, while deviations from the nominal values are modeled as random shocks with stochastic arrivals. Due to friction, the random shocks cannot be tracked by the main supply sources. Storage, on the other hand, is assumed frictionless as a supply source and can be used to compensate for the energy deficit shocks, though it cannot be filled up instantaneously. The storage control problem is formulated as an optimal control problem with the objective of maximizing system reliability. It is shown that when the stage cost is linear in the size of the energy deficit, the optimal control policy is myopic in the sense that all deficit shocks will be compensated up to the available level of storage. However, when the stage cost is strictly convex, it may be optimal to accept a small energy deficit in the interest of maintaining a higher level of reserve, which can help avoiding a large energy deficit in the future. The value of storage capacity in improving reliability, as well as the effects of the associated optimal policies under different stage costs on risk, i.e., the tail distribution of large energy deficits are examined.MIT-Siemens Cooperation: Optimal Control of Storage in Power SystemsMIT and Masdar Institute Cooperative Program (MIT-Masdar Initiative)National Science Foundation (U.S.) (Grant CPS-11358430

Design and implement of a low complexity in-band motion estimation circuit for wavelet-based moving picture coding

近年來小波轉換的延展性(scalability)被廣範的討論，基於小波影像的編解碼有2種做法，在小波域上(in-band)和空間域上(spatial)。本論文探討的是在小波域上的動態估測；最早提出這做法的是Zhang和Zafar，他們提出4種小波域上的動態估測演算法，但在小波域上的動態估測有移動變異效應(shift variance property)，所以我們提出一個部分低頻位移(PLBS)演算法來解決移動變異效應；部分低頻位移演算法方法跟低頻位移(LBS)相比所需記憶體降低60%，有效解決了傳統低頻位移所需記憶體太大的問題；而在動態估測運算複雜度上，運算複雜度和空間域相較，降低了90%。 在模擬結果中，我們發現在小波域上的動態估測在frame rate和畫面解析度較低的情況下，平均絕對值誤差(MAD)的表現要比時間域好；硬體實現方面，我們提出2個架構，改良式的-inter架構和改良式的- intra架構；改良式-inter為完全沒資料重覆利用(data reuse)，而改良式的- intra為level C的資料重覆利用(data reuse)，但改良式的- intra面積404kgate為改良式-inter的 9倍，消耗功率79.9mW也比改良式-inter的41.33mW來的大；在論文中有分析這2個架構的特性，從這些特性中可發現這2個架構的優缺點。In this thesis, We discuss the motion estimation of the wavelet domain; The motion estimation of wavelet domain scheme proposed by Zafar. They propose four wavelet domain of motion estimation algorithm, but in the wavelet domain of motion estimation have shift variant property, so in this thesis, we propose partial low band shift to slove shift variance property. Partial LBS compared with LBS reduce requirements memory 60%; and we proposed motion estimation computational complexity reduced 90% comparison with spatial domain. Simulation results show that the in-band motion estimation have good MAD when frame rate and resolution worse. In the ascept of hardware implemeation, we porposed two architecture Modified-inter architecture and Modified-intra architecture; Modified-inter architecture had no data reuse, and Modified-intra architecture is level C data reuse, but Modified-intra is the area of 404kgates for the nine times Modified-inter ; in this thesis, we analysis of this architcture of the two properties, from these characteristics can be found that the architecture of advantages.目錄 中文摘要 i 英文摘要 ii 目錄 iii 圖目錄 vi 表目錄 viii 第一章.緖論 1 1.1. 前言 1 1.2. 研究目的及動機 2 1.3. 論文架構 2 第二章.視訊壓縮編碼 4 2.1. 動態補償預測編碼(Motion Compensated Prediction) 5 2.1.1. 以離散餘弦轉換為基礎之MCP 5 2.1.2. 以離散小波轉換為基礎之MCP 8 2.2. 動態補償濾波器編碼(Motion Compensated Temporal Filter) 8 2.2.1. 基於時間域之動態補償編碼(t+2D) 9 2.2.2. 基於頻率域之動態補償編碼(2D+t) 9 2.2.3. Signal-based編碼系統比較 10 2.3. 小波轉換之編碼處理 11 2.3.1. ZTC演算法編碼過程 12 2.3.2. 微分脈衝編碼調變(DPCM)編碼技術 14 2.3.3. 小波轉換低頻部分的壓縮編碼模擬比較 15 第三章.補償離散小波轉換(ODWT) 16 3.1. 符號定義 16 3.2. ODWT 方法 16 3.3. 小波域之移動變異特性(shift variant property) 17 3.4. 低頻帶相位平移法(Low Band Shift scheme) 18 3.5. 比較DWT之ME/MC和ODWT之 ME/MC 22 3.6. 區塊效應 23 第四章.針對在小波域上低複雜度motion estimation設計 24 4.1. 部份LBS 方法 24 4.2. 小波區塊(wavelet block)之產生 25 4.3. 使用部份LBS方法之動態估測和補償 25 4.4. 模擬結果和分析 31 4.5. 移動估測之運算複雜度和記憶體分析 40 第五章.適用於小波域之低複雜度ME模組設計與硬體實現 42 5.1. 全區域動態估測之架構分析 42 5.1.1. inter-level and intra-level 42 5.1.2. Discussion the performance of the six previous works 43 5.2. On the data Reuse and Memory Bandwidth Analysis 46 5.2.1. Analysis of Data Reuse and Memory Accesses In Motion Estimation 46 5.3. 採用lifting 5/3濾波器之低複雜度ME硬體架構設計 51 5.4. Modified-inter 硬體架構 52 5.4.1. Modified-inter 硬體架構設計 52 5.5. Modified-intra 硬體架構 55 5.5.1. Modified- intra 硬體架構設計 56 5.5.2. Modified- intra Hardware operation 57 5.6. Modified-inter 和 Modified- intar之效能分析 60 5.7. 結論 63 第六章.結論與未來展望 64 第七章.參考文獻 65 圖目錄 圖. 1 1 Two level orvecomplete DWT of 1D signal 2 圖. 2 1數位壓縮技術之歸納(MCP：Motion Compensated Prediction) 4 圖. 2 2 Signal based video coder 5 圖. 2 3 DCT/Hybrid 編碼器 6 圖. 2 4 DCT/Hybrid 解碼器 6 圖. 2 5 H.264編碼器 7 圖. 2 6 H.264解碼器 7 圖. 2 7 MC-DWT編碼器 8 圖. 2 8 MC-DWT解碼器 8 圖. 2 9 Block diagram of the t+2D coding architecture 9 圖. 2 10 Block diagram of the 2D+t coding architecture. 10 圖. 2 11 MC-EZBC和H.26L之比較 11 圖. 2 12 in-band MCTF和spatial MCTF比較 (a)全解析度,全frame rate (b)1/2解析度,1/2 frame rate 11 圖. 2 13 Parent-offspring dependence with 3-level DWT 12 圖. 2 14 (a) The ZTC encoder scanning order 13 圖. 2 15零數編碼法金字塔結構之子母關係圖 14 圖. 2 16 DPCM pixel位置 15 圖. 3 1三階ODWT架構。 17 圖. 3 2 Shift variance of the Harr wavelet transform(Right signal shifted by one pixel to right, low & high pass coefficients in Harr DWT & ODWT) 18 圖. 3 3 1-D的Low-band-shift方法 19 圖. 3 4 Over-complete wavelet expansion using LBS algorithm for two level decomposition 20 圖. 3 5 Wavelet coefficients for the first frame of the “News” sequence using LBS algorithm 21 圖. 3 6 Interleaving of overcomplete wavelet coefficients for 1-level decomposition 21 圖. 3 7 Overcomplete wavelet coefficients of first frame of the “News” sequence using the interleaving algorithm 22 圖. 3 8 Block effect of spatial and wavelet domain 23 圖. 4 1 Fast low band shift method 24 圖. 4 2 Reorganization of the three-level wavelet coefficients into wavelet block 25 圖. 4 3 Garden sequence的spatial和LBS interpolation MAD曲線圖 26 圖. 4 4 Mobile sequence的spatial和LBS interpolation MAD曲線圖 27 圖. 4 5 圖解(1)方程式 28 圖. 4 6 圖解(2)和(3)方程式 30 圖. 4 7 Coastguard sequence使用不同濾波器PLBS(1)的MAD曲線圖 32 圖. 4 8 Coastguard sequence使用不同濾波器PLBS(2)的MAD曲線圖 33 圖. 4 9 Foreman sequence的MAD曲線圖(biorthognal 9/7 filter , CIF) 35 圖. 4 10 Hall monitor sequence的MAD曲線圖(biorthognal 9/7 filter , CIF) 36 圖. 4 11 Coastguard sequence的MAD曲線圖(lifting 9/7 filter , QCIF) 36 圖. 4 12 Hall monitor sequence的MAD曲線圖(lifting 9/7 filter , QCIF) 37 圖. 4 13 Coastguard sequence的MAD曲線圖(lifting 5/3 filter , QCIF) 37 圖. 4 14 news sequence的MAD曲線圖(lifting 5/3 filter , QCIF) 38 圖. 4 15 1/4 resolution Coastguard sequence的MAD曲線圖(lifting 5/3 filter , QCIF) 38 圖. 4 16 1/4 resolution hall monitor sequence的MAD曲線圖(lifting 5/3 filter , QCIF) 39 圖. 4 17 no.50 frame of Football sequence 39 圖. 4 18 Football sequence(50至100張)的MAD曲線圖(lifting 5/3 filter , CIF) 40 圖. 5 1 motion estimation algorithm through six nested loops 47 圖. 5 2 Level A schematic: local locality within candidate block strip. Level B schematic: local locality among adjacent candidate block strips. 48 圖. 5 3 Level C schematic: Global locality within search area strip. 49 圖. 5 4 Motion estimation block diagram 51 圖. 5 5 Architecture of PE 52 圖. 5 6 Overview of the proposed level 1 architecture 53 圖. 5 7 Whole architecture of the Modified-inter 55 圖. 5 8 overview of the architecture and the interconnection of PE ports Pin, Pout, SA, and SUM 56 圖. 5 9 PE structure 56 圖. 5 10 Data path of current data and the interconnections of ports AinT, AoutB, AinL, and AoutR. 57 圖. 5 11 Whole architecture of the Modified-intra 60 圖. 5 12 Hexagonal plot for the comparison of Modified-inter 62 圖. 5 13 Hexagonal plot for the comparison of Modified- intar 62 表目錄 表 2 1 ZTC符號定義 13 表 2 2小波轉換中低頻subband部分的壓縮編碼模擬 15 表 3 1 Average MAD of 100 frame for several video sequence 22 表 4 1 Sub-pix和LBS的MAD比較 26 表 4 2 100張 frame的MAD平均值使用biorthogonal 9/7濾波器 31 表 4 3 100張 frame的MAD平均值使用lifting 9/7濾波器 34 表 4 4 100張 frame的MAD平均值使用lifting 5/3濾波器 34 表 4 5 100張 1/4 resolution frame的MAD平均值使用lifting 5/3濾波器 35 表 4 6 Memory Complexity and Memory Requirements for motion estimation 40 表 5 1 Parallelism, Cycle, Latency of six hardware architectures[5.11] 43 表 5 2 Data Buffer and Memory Bit Width of six Hardware Architecture 43 表 5 3 Comparison of six Hardware Architecture 44 表 5 4 Bandwidth Requirement and data Reuse Level of Various Video 50 表 5 5 Local Memory Size for different reuse level of previous frame 51 表 5 6 Data flow for level 1 architecture 54 表 5 7 Data sequence of the search area pixels 58 表 5 8 Data sequence of the current block pixels 59 表 5 9 Parallelism, Cycle, Latency, and Utilization(The specification is 352*288,10fps) 61 表 5 10 Parallelism, Cycle, Latency, and Utilization of Modified-inter and SMT[5.13] 63 表 5 11 Parallelism, Cycle, Latency, and Utilization of Modified-intra and TJC 6