171 research outputs found
A novel scan segmentation design method for avoiding shift timing failure in scan testing
ITC : 2011 IEEE International Test Conference , 20-22 Sep. 2011 , Anaheim, CA, USAHigh power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling
It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC\u2799 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill.2011 Asian Test Symposium, 20-23 November 2011, New Delhi, Indi
Measurement of the 6Li(e,e'p) reaction cross sections at low momentum transfer
The triple differential cross sections for the 6Li(e,e'p) reaction have been
measured in the excitation energy region from 27 to 46 MeV in a search for
evidence of the giant dipole resonance (GDR) in 6Li. The cross sections have no
distinct structures in this energy region, and decrease smoothly with the
energy transfer. Angular distributions are different from those expected with
the GDR. Protons are emitted strongly in the momentum-transfer direction. The
data are well reproduced by a DWIA calculation assuming a direct proton
knockout process.Comment: 19 pages, 7 figures, revised text, to be published in Nucl. Phys.
Characteristics of a High-Purity Germanium Detector
開始ページ、終了ページ: 冊子体のページ付
Photo-production of neutral kaons on 12C in the threshold region
Kaon photo-production process on C has been studied by measuring
neutral kaons in a photon energy range of 0.81.1 GeV. Neutral kaons were
identified by the invariant mass constructed from two charged pions emitted in
the decay channel. The differential cross sections
as well as the integrated ones in the threshold photon energy region were
obtained. The obtained momentum spectra were compared with a Spectator model
calculation using elementary amplitudes of kaon photo-production given by
recent isobar models. Present result provides, for the first time, the
information on reaction which is expected to play an
important role to construct models for strangeness production by the
electromagnetic interaction. Experimental results show that cross section of
is of the same order to that of and suggest that slightly backward angular distribution
is favored in the process.Comment: 6 pages, 8 figure
A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing
High power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme.2011 IEEE International Test Conference, 20-22 September 2011, Anaheim, CA, US
Relativistic effects and two-body currents in using out-of-plane detection
Measurements of the reaction were performed
using an 800-MeV polarized electron beam at the MIT-Bates Linear Accelerator
and with the out-of-plane magnetic spectrometers (OOPS). The
longitudinal-transverse, and , and the
transverse-transverse, , interference responses at a missing momentum
of 210 MeV/c were simultaneously extracted in the dip region at Q=0.15
(GeV/c). On comparison to models of deuteron electrodisintegration, the
data clearly reveal strong effects of relativity and final-state interactions,
and the importance of the two-body meson-exchange currents and isobar
configurations. We demonstrate that these effects can be disentangled and
studied by extracting the interference response functions using the novel
out-of-plane technique.Comment: 4 pages, 4 figures, and submitted to PRL for publicatio
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.2015 IEEE 24th Asian Test Symposium (ATS), 22-25 November 2015, Mumbai, Indi
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.2008 13th European Test Symposium, 25-29 May 2008, Verbania, Ital
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