A New High Radix-2 r (r≥8) Multibit Recoding Algorithm for Large Operand Size (N ≥32) Multipliers

Abstract—This paper addresses the problem of multiplication with large operand sizes (N≥32). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier architecture for any size N of the operands. As a result, the critical path is drastically reduced to 3 2 3 3 N / − with no area overhead in comparison to modified Booth algorithm that shows a critical path of N/2 in adder stages. For instance, only 7 adder stages are needed for a 64-bit two’s complement multiplier. Confronted to reference algorithms for N=64, important gain ratios of 1.62, 1.71, 2.64 are obtained in terms of multiply-time, energy consumption per multiplyoperation, and total gate count, respectively

A New Recursive Multibit Recoding Algorithm for High-Speed and Low-Power Multiplier

Abstract—In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (n/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (ß≥8) multiplication. Based on a mathematical proof that any higher radix ß=2 r can be recursively derived from a combination of two or a number of lower radices, a series of generalized radix ß=2 r multipliers are generated by means of primary radices: 2 1, 2 2, 2 5, and 2 8. A variety of higher-radix (2 3- 2 32) two’s complement 64x64 bit serial/parallel multipliers are implemented on Virtex-6 FPGA and characterized in terms of multiply-time, energy consumption per multiply-operation, and area occupation for r value varying from 2 to 64. Compared to reference algorithm, savings of 8%, 52%, 63% are respectively obtained in terms of speed, power, and area. In addition, a new low-power and highly-flexible radix 2 r adapted technique for a multi-precision multiplication is presented