실리콘 나노와이어 트랜지스터에서의 표면 거칠기 충돌영향에 대한 이론연구

학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2013.2, [ vi, 55 p. ]In recent years, the bulk Si MOSFETs have reached the nanometric scale, leading to an increased density integration on chip, but also to a strong gate control in order to reduce the short-channel- effects (SCEs). In particular, using new materials instead of silicon or developing various device structures have been achieved for high performances in scaled devices. For this reason, the nanowire-based MOSFETs with the multi-gate type have become the most interesting candidates to replace actual planar MOSFET devices, expected to reduce SCEs. Especially, gate-all-around (GAA) structure has outstanding immunity to SCEs showing the best electrostatic control in the inversion layer which contributes to the transport property. One of the most important factor in considering transport properties in nanowire can be the surface roughness at the device/insulator interface and the easiest way to assess sub-10 nm device performance is the simulation work. Hence, we have computationally realized the surface roughness at the interfaces of the silicon nanowire transistors according to the autocorrelation function assuring that the surface roughness can be a significant scattering mechanism. In this thesis, we use a full quantum treatment to investigate the surface roughness-related physics and device transport characteristics by employing the non-equilibrium Green`s function (NEGF) approach. The overall characteristics of the low-field mobility and mean free path (MFP) are calculated with respect to the channel length (L), wire width (W), and the root-mean-square (RMS) of the surface roughness. Large amount of the mobility reduction for particularly small nanowire is observed, implying that the electrons near the rough interface experience more scattering as size is becoming smaller. And the behavior of the MFP with respect to the SR is investigated by the single parameter, RMS/W, showing that the MFP...한국과학기술원 : 전기및전자공학과

APPARATUS FOR TRANSISTOR OF USING METAL INSULATOR TRANSITION AND METHOD FOR MANUFACTURING THEREOF

금속 절연체 전이를 이용한 트랜지스터 및 이를 제조하는 방법이 개시된다. 일 실시예에 따른 트랜지스터는 서로 다른 물질이 적층된 기판; 상기 기판의 양 측에 형성되는 소스와 드레인; 및 상기 기판의 상단에 형성되며 압전 물질(Piezoelectric Material)로 이루어지는 게이트를 포함하고, 상기 게이트에 전기적 신호가 가해지는 경우, 상기 압전 물질에 의해 상기 기판은 변형(Strain)이 발생되어 상기 서로 다른 절연 물질이 적층된 경계면에 금속 절연체 전이(Metal-Insulator Transition)가 발생되고, 상기 금속 절연체 전이에 의해 채널이 형성되어 상기 소스와 상기 드레인 사이에 전류가 흐를 수 있다