메모리 소자를 위한 유기물과 탄소 나노튜브 기반의 전계 효과 트랜지스터에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 홍용택.With continued development in flexible and large area devices, there is increasing interest organic semiconductor materials and other semiconductor materials such as carbon based materials instead of traditional silicon based materials in electronic devices. These materials have intrinsic flexibility and versatile processing capability, which provide a broad range of applications in electronic device such as active-matrix organic light-emitting diode (AMOLED), logic circuit, and thin film transistors (TFTs) instead of conventional silicon based materials. Among these applications, TFTs are key elements for practical applications in flexible displays, logic circuits and memory applications such as memory transistors. In memory transistor devices, conventional thin films floating gate have been used for charge floating gate, but these conventional memory devices encounter difficulties of floating gate cell-to-cell interference and parasitic capacitance, and charge lossthese affect the overall device performance and reliability, when used with miniaturized cell sizes and in high densities. So many groups reported discrete nano-floating gate memory using metal nanoparticles such as gold nanoparticle because discrete nanoparticles have advantages that it is easy to control the trap density and distribution. Among the various potential candidates for the charge storage layer, graphene offers an advantage of introducing metallic properties. However, the two-dimensional continuous planar structure of graphene typically has difficulty in storing sufficient charge for non-volatile memory function, because the charge carrier stored in the continuous charge storage layer is easily lost through the thin tunneling dielectric. From this point, floating gate memory transistor using discrete charge floating gate are discussed by controlling synthesize of graphene in this thesis. We fabricated the graphene floating gate into the organic nonvolatile memory transistors (ONVMT) with bottom-gate/top-contact structure using pentacene and polystyrene (PS) as active and charge tunneling dielectric layers, respectively. For the floating gate, we proposed a discrete graphene layer formed by controlling growth time of the graphene layer during a conventional CVD process, and then simply transferring it onto the gate dielectric layer. The fabricated ONVMTs exhibited large memory windows (∼40 V) and a good data retention ability. The shift of the transfer curves at various gate biases indicated a clear charge-trapping and de-trapping behavior in the partially grown graphene within a short period of time (100 ms). The data retention properties of our devices showed an on/off ratio of about 5 × 104 even after 105 s, which leads to the estimated charge storage time of more than a year. The fabricated ONVMTs were reliable after more than one-hundred repeated programming/erasing cycle tests. Furthermore, we also fabricated SWCNT transistors based on inkjet printing technology for logic circuit applications. The carbon nanotubes (CNTs) has been widely studied for many aspects in recent years for their unique properties, which are valuable for nanotechnology, electronics, optics and other fields of materials science and technology. In particular, single-walled carbon nanotubes (SWCNTs) shows high electrical conductivity or semiconducting behavior according to their rapping direction. From these electrical properties, SWCNTs, especially semiconducting SWCNTs, have been expected to be used as alternative semiconducting material for field effect transistors. Based on these backgrounds, we illustrated SWCNT transistors based on inkjet printing technology for high performance and uniformity and illustrated advantages of inkjet printing method compared to other deposition method. For successful inkjet printing of SWCNTs solution, we optimized jetting conditions such as ink jetting velocity and drop-space. In SWCNT transistor, it is critical that the ink wets the targeted surface uniformly since networks of SWCNTs are formed during the drying of the ink. To deposit high density and uniform SWCNT films on substrate, we used surface treatment with poly-L-lysine (PLL) to enhance adhesion between SWCNTs and substrate. Also for source and drain in SWCNT transistor, we deposited Ag using inkjet printing method. Fabricated device showed high electrical performance and high uniformity without additional patterning. Also from this inkjet-printed SWCNT transistor, we fabricated SWCNT circuit applications including inverter and SRAM by using inkjet-printing method. For full-swing SWCNT inverter, we used chemical encapsulation with ammonium hydroxide (NH4OH). Also using this full-swing inverter, we fabricated SWCNT RAM by connecting two inverters input and output.Chapter 1 Introduction 1 1.1 Organic Non-Volatile Memory Transistors 1 1.2 Floating Gate Memory Transistors 5 1.3 Single-Wall Carbon Nanotube Transistors 11 1.4 Static Random Access Memory 14 1.5 Organization of This Dissertation 18 Chapter 2 Controlled Growth of a Graphene Charge-Floating Gate for Organic Non-Volatile Memory Transistors 23 2.1 Introduction 23 2.2 Materials and Processes 26 2.2.1 Graphene 26 2.2.2 Chemical Vapor Deposition Graphene 30 2.3 Experiments 33 2.4 Results and Discussion 36 2.5 Conclusion 53 Chapter 3 Inkjet-Printed Single-Wall Carbon Nanotube Transistors and Inverter 58 3.1 Introduction 58 3.2 Materials and Process 62 3.2.1 Single-Wall Carbon Nanotubes 62 3.2.2 Inkjet-Printing Systems 66 3.3 Inkjet-Printed SWCNT Transistors 68 3.3.1 Experiments 68 3.3.2 Results 71 3.4 Inkjet-Printed SWCNT Inverter 76 3.4.1 Experiments 77 3.4.2 Results 81 3.5 Conclusion 86 Chapter 4 Inkjet-Printed SWCNT Random Access Memory 90 4.1 Introduction 90 4.2 Inkjet-Printed Full-Swing SWCNT Inverter 92 4.2.1 Fabrication Process 92 4.2.2 Results 96 4.3 Inkjet-Printed SWCNT Static Random Access Memory 100 4.3.1 Fabrication Process 100 4.3.2 Results 104 4.4 Conclusion 108 Chapter 5 Conclusion 111 한글 초록 114Docto

A Study of Residential Segregation of the Foreign Population in the Seoul Metropolitan Area

외국인들이 어디에 얼마나 어떻게 거주하고 있는가의 문제는 국내체류외국인수의 급격한 증가로 나타나는 다양한 정책문제들을 진단하고 해결하기 위해 중요하게 다루어져야 할 주제이다. 하지만 그간 도시정책을 다룬 대부분 국내선행연구들은 실제 외국인집단과 내국인집단간의 거주지분리 정도를 측정하고 분석하는데 소홀하였다. 본 논문은 2009년 말 기준으로 수도권 3개 광역자치단체에 거주하는 외국인 인구들의 거주지 분리를 살펴보고자 한다. 분석결과 수도권 전체적으로 인천에 가까운 서쪽 지역들과 비교적 서울 중심에서 가까운 근교에 위치한 지역들에서 거주지분리의 정도가 높은 것으로 나타났다. 또한 외국인인구비율과 거주지분리정도를 비교한 결과 외국인들이 많이 사는 지역과 거주지분리가 심한 지역이 일치한다고 단정할 수 없었다. 따라서 현재 기존의 외국인인구 관련연구들이나 정부 정책들이 의존해왔던 주요 지표인 외국인인구비율과는 차별된 독자적인 지표로서 거주지분리를 측정하고 분석할 필요성을 확인하였다. The residential pattern of the foreign population is an important factor that must be dealt with in order to detect and resolve various policy problems caused by the rapid increase in the number of foreigners residing in Korea. However, most prior Korean urban research has failed to measure and analyze the level of residential segregation between foreign and local residents precisely. This present study aims to investigate the residential segregation of foreign residents for 78 local governments in the Seoul metropolitan area based on statistics from the end of 2009. According to the results, the level of residential segregation for foreign residents appears relatively high in some western regions near Incheon and in some suburbs very close to Seoul. In addition, it was difficult to conclude that areas where the percentage of foreign residents is high necessarily tend to match with areas with severe residential segregation. Thus, this paper confirms the necessity of measuring and analyzing residential segregation as an independent index, totally separate from the percentage of foreign residents that governmental policies and the current foreign population related literature have relied on

An Empirical Assessment of the Determinants of Municipal Cultural Policy Budgets: The Role of Budget Structure and Cultural Activity Type

최근 문화정책에 대한 관심은 꾸준히 증대하고 있지만 원활한 정책수행을 위해서 필수적인 문화예산에 대한 학문적 관심은 낮은 형편이다. 본 연구는 문화예산의 결정요인을 다룬 선행연 구들이 주목하지 않았던 예산의 재원구조와 문화 활동 유형에 초점을 맞추어 지방자치단체 문 화예산의 결정요인을 분석하고자 한다. 이를 위하여 전국 230개 기초자치단체를 분석단위로 2009년 문화예산자료와 다양한 시군구단위 자료들을 이용하여 ArcGIS의 지도그리기를 통한 탐색적 접근과 회귀분석모형을 통한 실증적 접근을 시도하였다. 분석결과 자치단체 문화예산의 규모가 예산 재원구조와 문화 활동 유형에 따라서 다른 것으로 나타났고 특히 수도권 지역과 지방간의 공간적 편차가 두드러졌다. 또한 문화예산에 영향을 미치는 요소들도 역시 예산 재원 구조 및 문화 활동 유형에 따라 상이한 패턴을 보이는 것을 확인하였다. 따라서 향후 문화예산 의 분석에 있어서 재원구조와 문화 활동 유형에 입각한 미시적 분석이 요구될 것이다. Despite increased public attention to cultural policy, scholarly interest in budget allocations for cultural policy remains low. As an attempt to address this dearth in extant literature, the objective of this research is to investigate the determinants of budget allocation for municipal cultural policies empirically, focusing in particular on budget structure and culture activity types that the previous literature has not considered. In pursuing the objectives of this research, an exploratory approach based upon ArcGIS mapping techniques was used as well as a regression analysis based on 2009 cultural budget data and various municipal statistics collected from 230 local governments from around the nation. The local government is the unit of analysis used in this study. Findings suggest that size of cultural budget in local governments vary according to budget structure and type of cultural activity. Moreover, there is a distinct spatial variation between the Seoul Metropolitan Area and other regions. The findings also suggest that the elements affecting the cultural budget differ according to budget structure and type of cultural activity. As such, the findings of this research suggest that more micro-level analysis, focusing on budget structure and type of cultural activity, is needed

비휘발성 유기 메모리 소자 응용을 위한 용액 공정기반 Graphene oxide 전하 저장층에 관한 연구

학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2012. 2. 홍용택.Since the past two decades, the interests of the organic thin film transistors (OTFTs) have been increasing for its many advantages including low-cost, largearea, light weight and flexible electronic applications. In organic electronics, organic light emitting diodes (OLEDs), organic field effect transistors (OFETs), organic nonvolatile memory devices (ONVMs) and organic photovoltaic cells have been investigated. Among these organic electronic devices, organic nonvolatile memory transistors (ONVMTs) role is increasing because they are the integral component in all of these applications. In these ONVMTs, floating gate ONVMTs are one of the most widely used memory transistors because of their versatility in modulating device performance by modifying both the tunneling layer and charge trap layers. To date, Au metal nanoparticles and Al thin film have been used as charge trap layer and charge tunneling layer. However, this process costs high because this needs vacuum environments. So many researchers have been ying to find proper materials to use in tunneling layer and charge trap layer. Among the candidates, graphene oxide (GO) was reported as a candidate for charge trap layer. When GO was formed in thin layer, it was reported this GO sheets have charge storage capacity for memory applications. This GO has advantages that it can be solution-processed via spin coating because GO has solubility in deionized water or dimethylformamide (DMF). Solution process can reduce the cost and the complexity of the deposition compared to vacuum process. In this study, we fabricated and evaluated two ONVMTs with polymethylmethacrylate (PMMA) charge tunneling layer, one is ONVMTs with GO and another is ONVMTs without GO to confirm charge trap ability in GO. From experiment, ONVMTs with GO showed threshold voltage shift when we applied gate bias but ONVMTs without GO didnt show threshold voltage shift in the same condition. So we could know that GO has charge storage ability. In addition, we fabricated GO based ONVMTs using polyv yl phenol (PVP) as charge tunneling layer and evaluated its properties. GO based ONVMTs using PVP as charge tunneling layer showed threshold voltage shift under gate bias, but compared to GO based ONVMTs using PMMA as charge tunneling layer, ONVMTs using PVP showed worse performance in memory window and retention time.최근 20년 동안, 유기 박막 트랜지스터에 대한 관심이 증가하고 있다. 이러한 관심의 증가의 이유로는 유기 박막 트랜지스터의 제조 과정상의 낮은 비용, 대면적화, 가벼운 무게, 그리고 유연한 기판의 사용 가능하기 때문이다. 이러한 유기 전자 소자들 중, 유기 발광 소자 (OLED), 유기 전계 효과 트랜지스터 (OFET), 유기 비휘발성 메모리 소자 (ONVM), 유기 광전변환 셀 등에 대한 연구가 활발하게 진행되고 있다. 이 중, 특히 유기 비휘발성 메모리 소자의 중요성이 증가되고 있는데 이는 모든 전자 소자의 응용 분야에 필수적인 요소이기 때문이다. 이러한 비휘발성 메모리 소자들 중에서 구조적인 단순함과 전자 저장 층과 전자 통과 층의 조절이 간편하기 때문에Floating 게이트 유기 발광 메모리 소자가 가장 널리 사용된다. 그 중 gold nanoparticle이 전하 저장 층으로 가장 널리 사용되고 있는데, 이러한 gold nanoparticle은 진공 공정을 필요하기 때문에 가격이 비싸고 공정 과정이 복잡하다는 단점을 가진다. 또한 전하 통과 층으로는 얇은 Al 막을 널리 사용하는데 이도 gold nanoparticle과 마찬가지로 공정 과정이 복잡하고 비용이 많이 든다는 단점이 있다. 이러한 단점을 해결하기 위해 전하 저장 층과 전하 통과 층에 대한 개발이 진행되어 왔다. 이러한 노력의 결과 graphene oxide가 전하 저장 층으로 사용 가능하다는 연구 결과를 바탕으로 유기 비휘발성 메모리 소자의 연구가 진행되고 있다. 이러한 graphene oxide를 이용하면 gold nanoparticle과는 달리 deionized water나 dimethyl-formamide (DMF)에 분산이 가능하므로 용액 공정을 할 수 있어 공정을 단순화 할 수 있고 또한 이를 통해 공정의 비용을 절감할 수 있게 된다. 본 연구에서는 이러한 용액 공정을 이용하여 graphene oxide기반의 유기 비휘발성 메모리 소자를 만들었다. 먼저 graphene oxide의 전하 저장 층으로써의 활용 가능성을 확인하기 위해 polymethylmethacrylate (PMMA) 를 전하 통과 층으로 이용하여 graphene oxide 층이 있는 소자와 없는 소자를 만든 후 비교를 통해 확인하였다. 이 연구를 통해 graphene oxide가 전하 저장 층으로 사용 가능하다는 것을 확인 할 수 있었다. 또한 전하 polyvinyl phenol (PVP) 의 전하 통과 층으로써의 기능을 확인해 보기 위해 위와 마찬가지의 방법으로 전하 저장 층으로써 graphene oxide 층이 있는 소자와 없는 소자를 만든 후 비교해 본 후 위에서 만든 PMMA 를 전하 통과 층으로 사용한 소자와 비교해 보았다. 그 결과 PMMA를 전하 통과 층으로 사용한 소자의 경우가 PVP를 전하 통과 층으로 사용한 소자보다 retention time과 memory window 측면에 있어서 보다 나은 특성을 보였다.Maste