거더의 상대 변위를 고려한 다중 거더 교량의 유한요소 모델 개선

학위논문 (박사)-- 서울대학교 대학원 공과대학 건설환경공학부, 2017. 8. 고현무.운용중인 교량 구조물은 노후화, 극한상황에 따른 피해 등으로 인해 부재의 열화를 겪는다. 즉, 각 부재의 탄성계수, 단면 넓이 등 구조 변수값은 설계도면상의 그것과 달라지게 되며 그로 인해 교량의 구조적 성능 또한 지속적으로 변화한다. 이러한 교량을 안전하고 비용효율적으로 유지관리하기 위해서는 구조물의 현재 성능에 대한 정확한 평가가 선행되어야 한다. 최근 교량의 구조 성능을 나타내는 객관적인 지표로서 Load Rating factor(RF)를 사용하는 경우가 증가하고 있다. RF는 구조물의 활하중효과에 대한 내하력의 비율을 수치로 나타낸 것이기 때문에, 다른 방식들에 비해 정량적이고 객관적이라는 점에서 우수성을 보인다. RF를 정확하게 산정하기 위한 한 가지 방법은 유한요소해석을 이용하는 것이다. 이를 위해서는 초기 설계도서에 기반하여 교량의 유한요소모델을 구성한 후, 운용 중 교량의 거동을 계측하여 교량의 현재 상태를 반영하도록 업데이트해야 한다. 일반적으로 유한요소모델 업데이트를 위해서는 차량재하시험을 수행한다. 그로부터 거더의 처짐, 변형률 등 부재단위 응답을 계측한 후, 수치해석으로부터 얻은 응답과의 오차가 최소화되도록 유한요소모델의 구조변수값을 수정하는 최적화 과정을 거친다. 하지만 이 방법은 공용중인 교량에 대한 전면적인 교통 통제 등 사회/경제적 비용을 크게 요구한다는 단점이 있다. 이에 대한 대안으로 상시진동시험으로부터 얻을 수 있는 고유진동수, 모드형상 등의 동적 응답만으로 유한요소모델을 업데이트하는 방법도 있다. 하지만 이 방법을 통해 전역적인 거동에 대한 대략적 정보를 얻을 수는 있어도, 부재 단위의 강성정보를 얻는 것은 한계가 있다. 특히 유한요소해석을 통해 RF를 산정할 때에는 부재단위의 정확한 업데이트가 요구되기 때문에, 상시진동데이터를 이용해 업데이트한 모델로는 한계가 있음이 지적되어 왔다. 이 논문은 교량의 거더 간 상대적 처짐 (Relative Girder Displacement, RGD)개념을 도입하여, 상시진동데이터를 이용한 유한요소모델 업데이트의 정확도를 향상시키는 방안을 제시한다. RGD는 동적 및 정적 하중에 대해 거의 동일한 값을 나타내며 부재단위의 강성 정보를 제공하기 때문에 기존의 한계를 극복할 수 있을 것으로 생각되었다. 그리고 MAC과 유사하게 벡터로서 형상을 표현하는 Relative Girder Displacement Assurance Criterion (RGDAC)개념을 정의함으로써 개별적인 값으로 표현되는 RGD의 단점을 보완하였다. RGD와 RGDAC를 이용하여 목적함수를 구성하는 방식을 다양화하며 각각이 모델 업데이트에 미치는 영향을 분석함으로써 높은 모델을 얻기 위해 가장 적합한 목적함수 설정 방법을 제안한다. 제안된 방법을 검증하기 위해 실교량에 기반한 가상 교량모델을 구성하고 모델 업데이트를 수행했다. 임의의 부재에 대해 강성의 저하를 가정하고, 다양한 목적함수를 설정해 업데이트한 결과 제안하는 방법의 우수함을 보일 수 있었다. 또한 하중의 위치를 달리하여 업데이트효과를 검증함으로써 제안된 방법의 일반성을 확인하였다. 적용성을 보이기 위한 예제로서 실험 데이터를 이용한 실교량의 유한요소모델 업데이트를 수행했다. 또 업데이트된 모델을 이용하여 RF를 산정함으로써 제안된 방법의 실제적인 활용을 보여주었다.Bridge in operation experiences deteriorations due to various factors such as aging and damages, and the structural performance of a bridge thus changes continuously over its lifetime. For safe operation and cost-effective maintenance of the bridge, precise evaluation of current performance of the bridge is essential. Recently as an index of the performance of bridge, Load Rating Factor (RF) is regarded as quantitative and objective in comparison with other typically-used methods. RF is usually calculated by finite element (FE) analysis in which a baseline FE model needs to be updated using field measurement which can portray the actual structural behavior. Generally, load testing is conducted in order to update FE model. On the other hand, FE models can also be updated using an ambient vibration data without performing costly load testing. However, But it has a limitation that individual stiffness information of each member or local level, which can affect greatly the accuracy of RF, is difficult to be attained. This study proposes a new finite element model updating method using ambient vibration data which can enhance the accuracy of updated FE model by adapting Relative Girder Displacement (RGD) and Relative Girder Displacement Accuracy Criterion (RGDAC) concepts. RGD and RGDAC can be regarded as a supplementation to each other because RGD is defined as individual values while RGDAC represents shape with a vector. The two indices are embedded into objective function of optimization in FE model updating procedure, and optimal form of an objective function with RGD and RGDAC is obtained from various numerical simulations. In order to verify the proposed method, a simulated bridge model is created based on an existing bridge. FE model is updated according to proposed method in order that its response becomes closer to that of simulated bridge model. The updated model shows good agreement with simulated bridge model with assumed stiffness deterioration. The generality of the proposed method is confirmed by verifying the results for the cases under various lane load locations. As an illustrative example, FE model for an actual existing bridge is composed and updated by using dynamic displacement data. With the updated FE model, RF is calculated to confirm the proposed method and show its practical application.Chapter 1. Introduction 1 1.1 Research Background 1 1.2 Literature Survey 2 1.3 Research Objectives and Scope 4 1.4 Overview of Dissertation 6 Chapter 2. Finite Element Model Updating using Relative Girder Displacement 7 2.1 Relative Girder Displacement of Multi-girder Bridges 7 2.1.1 Advantage of using the Relative Girder Displacement for Finite Element Model Updating 7 2.1.2 Definition of Relative Girder Displacement 9 2.1.3 Acquisition of the Relative Girder Displacement from Measurement Data 10 2.2 Relative Girder Displacement Index for Updating Finite Element Model 12 2.2.1 Relative Girder Displacement Index 12 2.2.2 Relative Girder Displacement Assurance Criterion 15 2.3 Formulation of the Finite Element Model Updating using Relative Girder Displacement Indices 15 2.3.1 Error Function for Value of Modal and Static Displacement 16 2.3.2 Error Function of the Relative Girder Displacement 18 2.3.3 Error Function of the Relative Girder Displacement Assurance Criterion 19 2.3.4 Objective Function for Updating Finite Element Model 20 2.3.5 Illustrative Example: Error Function of the Relative Girder Displacement 22 2.3.6 Illustrative Example: Error Function of the Relative Girder Displacement Assurance Criterion 26 2.4 Summary 27 Chapter 3. Numerical Evaluation of the Proposed Method 29 3.1 Example using Multi-Girder Bridge Structure 30 3.1.1 General Description of the New Jersey Bridge 30 3.1.2 Sophisticated Finite Element Model of New Jersey Bridge 36 3.2 Baseline Finite Element Model and Simulated Bridge Model 39 3.2.1 Baseline Finite Element Model based on the Sophisticated Finite Element Model 39 3.2.2 Virtual Measurement Data from the Simulated Bridge Model 42 3.3 Finite Element Model Updates through an Optimization Procedure 44 3.3.1 Selection of Optimization Parameters 44 3.3.2 Optimization Algorithm 47 3.4 Comparison of Update Performances of Various Objective Functions 49 3.4.1 Description of Virtual Measurement Data 49 3.4.2 Formulation of Objective Functions 51 3.4.3 Comparison of Structural Responses 53 3.4.4 Evaluation of Load Rating 58 3.5 Update Performance of the Proposed Method for Various Lane Loading Cases 59 3.5.1 Description of Virtual measurement data 59 3.5.2 Formulation of Objective Functions 61 3.5.3 Comparison of Structural Responses 64 3.5.4 Evaluation of Load Rating 69 3.6 Updating the Performance of the Proposed Method for Various Cases of the Girder Stiffness Distribution 71 3.6.1 Description of the Virtual measurement data 71 3.6.2 Formulation of Objective Functions 73 3.6.3 Comparison of Structural Responses 74 3.6.4 Evaluation of Load Rating 76 3.7 Summary 78 Chapter 4. Application Example for a Real Bridge Structure 81 4.1 General Description of Yeondae Bridge 81 4.2 Field Loading Tests 83 4.3 Development of the Baseline Finite Element Model 88 4.4 Finite Element Model Updating Using the Proposed Method 89 4.4.1 Selection of Optimization Parameters 89 4.4.2 Formulation of Objective Functions 92 4.5 Bridge Performance Evaluation 94 4.5.1 Comparison of the Structural Responses 94 4.5.2 Evaluation of Load Rating 97 4.6 Summary 98 Chapter 5. Conclusion 100 References 103 Abstract in Korean 117Docto

Methods for Threshold Voltage Setting of String Select Transistors in Channel Stacked NAND Flash Memory

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 박병국.Since recent mobile electronic devices such as tablets, laptops, smartphones, or solid-state drives (SSDs) have started to adopt the NAND flash memory as their main data storage device, the demand for low-cost and high-density NAND flash memories has experienced a rapid increase. However, some problems such as the limitations of photolithography technology, cell-to-cell interference, and reduction of the number of electrons stored in floating gates have hindered the downscaling of floating-gate NAND flash memories. To overcome the NAND scaling issues, several types of three-dimensional (3D) stacked charge-trap NAND flash memories, which have been developed based on the bit-cost scalable (BiCS) technology introduced by Toshiba, have been widely investigated, owing to their scalability, ease of fabrication, and coupling-free characteristics. 3D-stacked NAND flash memory architectures can be divided into two categories. The first is the gate-stacked NAND flash memory, in which current flows through a vertical channel while the gates are shared horizontally by all the strings. The second category consists of channel-stacked NAND flash memories, in which the current flows through the horizontally stacked channel and the gates are shared vertically by all the strings. In 3D-stacked NAND flash memory architectures. The channel-stacked type presents several outstanding advantages in terms of minimal unit cell size, bit line (BL) pitch scaling, use of a single-crystalline Si channel by Si/SiGe epitaxial growth process, and degradation characteristics of read currents caused by the increase in the number of stacked layers. However, compared with the gate-stacked type, the channel-stacked type presents critical issues that hinder its use in commercial applications, such as complex array architectures and decoding of the stacked layers. To overcome these problems, our group has recently reported channel-stacked arrays with layer selection by multilevel (LSM) operation. However, the array architecture and operation scheme setting the string select transistors (SSTs) with multilevel states should be simplified further to enable commercialization. In this dissertation, a simplified channel-stacked array with LSM operation is proposed. In addition, new SST threshold voltage (Vth) setting methods to set all the SSTs on each layer to the targeted Vths values are introduced and verified by using technology computer-aided design (TCAD) simulations and measurements in fabricated pseudo-SLSM. Furthermore, various disturbance phenomena that could occur during basic memory operations such as erase, program, and read are analyzed, and schemes for mitigating these disturbances are proposed and verified.Chapter1 Three-Dimensional Stacked NAND Flash Memory 1 1.1 Introduction to Three-Dimensional Stacked NAND Flash Memory 1 1.2 Gate Stack Type NAND Flash Memory 8 1.3 Channel Stack Type NAND Flash Memory 17 1.4 Comparison between Gate Stack Type NAND Flash and Channel Stack Type NAND Flash 24 Chapter2 Channel Stacked NAND Flash Memory with Layer Selection by Multilevel Operation 28 2.1 LSM and Channel Stacked NAND Flash Architecture Design 28 2.2 Operation Scheme of Channel Stacked NAND Flash Memory with LSM 36 2.2.1 Stacked SST Initialization to Enable LSM 36 2.2.2 Read Operation with LSM 38 2.2.3 Program/Erase Operation with LSM 42 2.3 Comparison with Conventional Channel Stacked NAND Flash Memory Architecture 47 Chapter3 Methods for Setting String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory 50 3.1 Method for Setting SST Vth Using One Erase Operation 50 3.2 Method for Setting SST Vth Using Dummy SSTs 60 Chapter4 Reliability Issues During LSM in Channel Stacked NAND Flash Memory 69 4.1 Program Disturbance in SLSM 69 4.2 Read Disturbance in SLSM 84 Chapter5 Application to General NAND Flash Memory 95 Chapter6 Conclusions 103 Bibliography 106 Abstract in Korean 119Docto