Inductorless CMOS Receiver Front-End Circuits for 10-Gb/s Optical Communications

[[abstract]]In this paper, a 10-Gb/s inductorless CMOS receiver front end is presented, including a transimpedance amplifier and a limiting amplifier. The transimpedance amplifier incorporates Regulated Cascode (RGC), active-inductor peaking, and intersecting active feedback circuits to achieve a transimpedance gain of 56 dB and a bandwidth of 8.27 GHz with a power dissipation of 35 mW. The limiting amplifier employs interleaving active feedback to achieve a differential voltage gain of 44.5 dB and a bandwidth of 10.3 GHz while consuming 226 mW. Both circuits are realized in 0.18- m CMOS technology with a 1.8-V supply.[[notice]]補正完畢[[incitationindex]]EI[[booktype]]紙

A low power sigma-delta modulator for dual-mode wide-band receiver

[[abstract]]This work presents a low power cascaded sigma-delta modulator for GSM and WCDMA applications. The proposed modulator has the characteristics of wide bandwidth for WCDMA applications and low distortion in the low frequency band for GSM applications. Low-distortion and interpolative techniques are used in this modulator to enhance the performance. The low-distortion technique has not only the swing-suppressing characteristic, but it can reduce the power consumption. Moreover, the resolution can be improved even under non-linearity effects. An experimental chip is implemented in the standard 0.18-μm 1P6M CMOS technology. The measurements indicate a dynamic range of 76/68 dB and a peak signal to noise plus distortion ratio of 70/61 dB for GSM/WCDMA applications. The core area is 1 × 1.4 mm2 and the power consumption is 10.5/28 mW for GSM/WCDMA at 1.8 V.[[incitationindex]]SCI[[booktype]]紙

A low-offset low-noise sigma-delta modulator with pseudorandom chopper-stabilization technique

[[abstract]]This paper presents a low-offset low-noise sigma-delta modulator with pseudorandom chopper-stabilization technique. The comparison of the noise-cancellation ability with the correlated double sampling and chopper-stabilization techniques is demonstrated; also, the noise performance of these cancellation techniques is observed and discussed. Using the proposed technique, the modulator achieves 92 dB of dynamic range and -135 dB of noise floor while consuming 950 ??W from a 3-V supply. Based on the experimental results, the pseudorandom chopper-stabilization technique has a DC offset voltage that is 6 dB lower than that of the chopper-stabilization technique, and retains a thermal noise floor that is 1.6 dB lower than that of the correlated double sampling technique.[[incitationindex]]SCI[[booktype]]紙