Power Optimization in Johnson Counter through Clock Gating with Static Energy Recovery Logic

In the latest designs of VLSI, power dissipation is the main charge to take care. The dependency on micro electronics is rising as the size of chip is being compact & also the systems with minimal power are being prioritized. The computer systems are comprised of sequential circuitries & this is the reason that designs having minimal power absorption gave gained priority. In this document, we have suggested a schema on minimal power of Johnson Counter by employing a clock gating system & pass transistors in D flip flop. By making few judgements on power in SPICE, it is presumed that he suggested system design leads to minimal power decadence & has simple interlinking in contrast to the complicated traditional designs. In this document we put the outcomes of power in contrast in four methods that are TG ADCL i.e. Adiabatic Dynamic CMOS Logic, TG QSERL i.e. Quai static energy recovery logic, TG normal & TG split level pulse. Power has risen too high in TG ADCL, TG QSERL & TG normal