Zero-Skew Clock-Tree Optimization with Buffer-Insertion/Sizing and Wire-Sizing

International audienceWell-aligned ZnO nanorods (NRs) have been synthesized by chemical bath deposition (CBD) method on (100) p-type Silicon substrate for various growth times. ZnO seed layers have been pre-coated on Si by sol-gel spin-coating process. The effect of growth time on structural, morphological and electrical properties of ZnO NRs were systematically investigated by X-Ray diffraction, scanning electron microscopy and current-voltage measurements at room temperature. SEM images illustrated that vertical, well-aligned, uniformly distributed, dense ZnO NRs were observed to grow on the Si substrate. Moreover, the growth rate decreases dramatically as the deposition time increased. X-ray diffraction pattern showed that the synthesized ZnO NRs have hexagonal wurtzite structure and exhibit a preferred orientation along the c-axis. The current–voltage analysis provided information about electrical parameters of n-ZnO NRs/p-Si heterojunction diode as a function of the growth time. The results showed an increase in the barrier height ϕb and a decrease in the ideality factor n, as the length of the NRs increased. More details about I–V characteristics measured under illumination and in the dark are also reported

Zero Skew Clock-Tree Optimization with Buffer Insertion/Sizing and Wire Sizing

Cloc distribution iscvV(Nj for timing and designcsi vergenc in high-performanc very largescVN integration designs. Minimum-delay/power zero skew buffer insertion/sizing and wire-sizing problems have long beencenvVjV ed intracv2(V) In this paper, we presentClm kTune, a simultaneous buffer insertion/sizing and wire-sizing algorithmwhic guarantees zero skew and minimizes delay and power in polynomial time. Extensive experimental results show that our algorithm execrit very efficvN----P . For example,ClI kTuneacv6 ves 45 delay improvement for buffering and sizing an industrialcndu tree with 3101 sink nodes on a 1.2-GHz Pentium IV PC in 16 min,cn,vV ed with the initial routing. Our algorithmco also be used toacVU ve usefulcefu skew to facUNV:v2 timingcm vergenc and toinc ementally adjust thecev6 tree for designcs vergenc and explore delay--power tradeoffs during designcs csi Cl kTune is available on the web (http://vlsi.ecvvVN)(Vv2--6 ools.htm). Index Terms---Buffer insertion, buffer sizing,czin tree, optimization, wire sizing, zero skew