Wordlength optimization for linear digital signal processing

Published versio

SWATI: Synthesizing Wordlengths Automatically Using Testing and Induction

In this paper, we present an automated technique SWATI: Synthesizing Wordlengths Automatically Using Testing and Induction, which uses a combination of Nelder-Mead optimization based testing, and induction from examples to automatically synthesize optimal fixedpoint implementation of numerical routines. The design of numerical software is commonly done using floating-point arithmetic in design-environments such as Matlab. However, these designs are often implemented using fixed-point arithmetic for speed and efficiency reasons especially in embedded systems. The fixed-point implementation reduces implementation cost, provides better performance, and reduces power consumption. The conversion from floating-point designs to fixed-point code is subject to two opposing constraints: (i) the word-width of fixed-point types must be minimized, and (ii) the outputs of the fixed-point program must be accurate. In this paper, we propose a new solution to this problem. Our technique takes the floating-point program, specified accuracy and an implementation cost model and provides the fixed-point program with specified accuracy and optimal implementation cost. We demonstrate the effectiveness of our approach on a set of examples from the domain of automated control, robotics and digital signal processing

Non-uniform wordlength delay lines for FIR filters

When FIR filters are designed floating point arithmetic is generally used. However when implemented on hardware such as ASICs, fixed point arithmetic must be used to minimise cost and power requirements. Research to minimise hardware costs has mainly focused on the quantization effects of fixed point wordlengths for the coefficients, multipliers and adders of FIR filters, but with the actual data delays assigned a uniform wordlength and essentially not optimised. This paper proposes that the wordlengths of the delay line can be non-uniform with a minimal increase in quantization noise for parallel implementation of FIR filters where there are differences in the magnitudes of the coefficients. A non-uniform delay line allows hardware savings in terms of delay register wordlengths, delay signal wordlengths and multiplier wordlengths. Results for an FIR design are presented which demonstrate the hardware savingswhen using a non-uniform wordlength delay lin

Design of Multistage Decimation Filters Using Cyclotomic Polynomials: Optimization and Design Issues

This paper focuses on the design of multiplier-less decimation filters suitable for oversampled digital signals. The aim is twofold. On one hand, it proposes an optimization framework for the design of constituent decimation filters in a general multistage decimation architecture. The basic building blocks embedded in the proposed filters belong, for a simple reason, to the class of cyclotomic polynomials (CPs): the first 104 CPs have a z-transfer function whose coefficients are simply {-1,0,+1}. On the other hand, the paper provides a bunch of useful techniques, most of which stemming from some key properties of CPs, for designing the proposed filters in a variety of architectures. Both recursive and non-recursive architectures are discussed by focusing on a specific decimation filter obtained as a result of the optimization algorithm. Design guidelines are provided with the aim to simplify the design of the constituent decimation filters in the multistage chain.Comment: Submitted to CAS-I, July 07; 11 pages, 5 figures, 3 table

Optimal controllers for finite wordlength implementation

When a controller is implemented in a digital computer, with A/D and D/A conversion, the numerical errors of the computation can drastically affect the performance of the control system. There exists realizations of a given controller transfer function yielding arbitrarily large effects from computational errors. Since, in general, there is no upper bound, it is important to have a systematic way of reducing these effects. Optimum controller designs are developed which take account of the digital round-off errors in the controller implementation and in the A/D and D/A converters. These results provide a natural extension to the Linear Quadratic Gaussian (LQG) theory since they reduce to the standard LQG controller when infinite precision computation is used. But for finite precision the separation principle does not hold

The digital implementation of control compensators : the coefficient wordlength issue

Bibliography: leaves 32-34."October, 1979."NASA Ames Grant NGL-22-009-124by Paul Moroney, Alan S. Willsky, Paul K. Houpt

Optimum wordlength allocation

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On the Implementation of Efficient Channel Filters for Wideband Receivers by Optimizing Common Subexpression Elimination Methods

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Roundoff noise minimization in a modified direct-form delta operator IIR structure

Among various direct-form delta operator realized filter structures, the delta transposed direct-form II (δDFIIt) has been shown to produce the lowest roundoff noise gain in finite wordlength implementations. Recent analyses focus on the optimization of the free parameter Δ of the delta operator, with scaling of the structure to prevent arithmetic overflow. This paper proposes a modified δDFIIt second-order section in which the Δs and filter coefficients at different branches are separately scaled to achieve improved roundoff noise gain minimization. Expressions for the filter coefficients are derived, and reduction of roundoff noise gain is verified by numerical examples.published_or_final_versio

The wordlength determination problem of linear time invariant systems with multiple outputs - A geometric programming approach

IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, 21-24 May 2006This paper proposes two new methods for optimizing hardware resources in finite wordlength implementation of multiple-output (MO) linear time invariant systems. The hardware complexity is measured by the exact internal wordlength used for each intermediate data. The first method relaxes the wordlength from integer to real-value and formulates the design problem as a geometric programming, from which an optimal solution of the relaxed problem can be determined. The second method is based on a discrete optimization method called the Marginal Analysis method, and it yields the desired wordlengths in integer values. By combining these two methods, a hybrid method is also proposed, which is found to be very effective for large scale MO systems. Design example shows that the proposed algorithms offer better results and a lower design complexity than conventional methods. © 2006 IEEE.published_or_final_versio